Service manual

Cache Coherency B-17
Victim and Q1 Ordering
To properly implement memory barriers, the cache coherency protocol requires
that victim packets “push” Q1 packets from the H-switch arbitration point to
the output of the victim’s home QS Arb.
8. The H-switch orders all incoming Q1 packets and victim packets for each of
its output ports. All Q1 and victim packets from the H-switch must appear
at the output of their targeted QS Arb such that all Q1 packets that
preceded a given victim as the packets were issued from the H-switch, still
precede the same victim as the packets are issued from the QS Arb.
QIO Full Ordering
9. All PIO reads and PIO writes from a common processor to a common
I/Odevice must appear in the same order at the I/Odevice as the order in
which they are issued from their processor.
QIO and Q1 Ordering
To properly implement a cached IOP, the cache coherency protocol requires that
QIO packets “push” Q1 packets from the H-switch arbitration point to the
output of the QIO packet’s home QS Arb.
10. The H-switch merges all incoming Q1 packets and QIO packets into a single
order, one for each H-switch output port. All Q1 and QIO packets from the
H-switch must appear at the output of their targeted QS Arb such that all
Q1 packets that preceded a given QIO packet as the packets were issued
from the H-switch, still precede the same QIO packet as the packets are
issued from the QS Arb.