Service manual

B-16 AlphaServer GS80/160/320 Service Manual
5. When ordered lists of Q1 packets from multiple HS input ports target
multiple common HS output ports, the Q1 packets must appear at the
output ports in a manner consistent with a single, common ordering of all
incoming Q1 packets. Each output port may transmit some or all of the
packets in the common ordered list.
Q0 Read and Victim Ordering
The system enforces ordering restrictions on reads and victims from the same
processor to the same memory block. This restriction applies to the situation
where a processor executes the following sequence of events:
1. Read Y, causing Victim X.
2. Read X.
The ordering rule for victim X and read X is:
6. Reads and victims from the same processor to the same memory block must
appear at the output of the QS Arb of the memory block’s home QBB in the
same order in which they were issued by the processor.
Q0 Change-to-Dirty and Read Ordering
Cache coherency protocol requires that before a change-to-dirty command
targeting a given address can be forwarded from the GPA TTT, no reads to
same address can be in the round trip path between the particular TTT and the
address’ home directory. Since the intent of this rule is to have Change-to-
Dirty commands arrive at their home directory without Read commands to the
same address in front of them in the round trip path, a TTT ordering function
alone is not sufficient for proper system operation. It must be combined with
the following system ordering rule:
7. All change-to-dirty and read commands to the same address from the same
QBB must appear in the same order at the output of their destination QS
Arb as the order in which their source TTT issued them.