Service manual

Cache Coherency B-15
B.8 Virtual Channel Ordering Rules
To support cache coherency, virtual channels obey a number of ordering rules.
These rules are enforced:
• To support “Sparse Vector” directories (i.e. 1 directory bit/QBB vs. 1
directory/processor)
• To enable system support of Memory Barriers.
• To minimize permutations of in flight transactions.
Q1 Full Ordering
At each QBB, the main arbiter in the QSA, the QS Arb, orders all Q0
transactions to the QBB’s home memory space. This in turn generates a serial
stream of Q1 packets directed at both the processor local to the QBB and
processors remote to the QBB. These two streams of Q1 packets obey the
following rules:
1. All Q1 packets generated by any given QS Arb are generated in a serial
order. All processors targeted by some or all of the Q1 packets from a given
QS Arb must see these Q1 packets in the order that they were generated.
2. All Q1 packets targeted at processors in QBBs, other than the home QBB,
must pass through the QS Arb of the target QBBs. Each QS Arb at each
target QBB put Q1 packets from other QBBs with the Q1 packets they
generate from Q0 packets in some order. All local processors targeted by
some or all of the local Q1 packets and remote Q1 packets must see all of
these packets in the order that the local QS Arb put them in.
This rule does not dictate specific ordering of Q1 packets from one QS Arb
and Q1 packets from another QS Arb. While the ordering of packets is
somewhat arbitrary, it is constrained by 4 rules. The first rule pertains only
to ordering between Q1 packets sent from a QS Arb to its local processor
and Q1 packets sent from a remote QS Arb. The latter 3 rules pertain to the
ordering of Q1 packets as they cross the hierarchical switch.
3. If multiple Q1 packets from a given H-switch input port are targeted at a
common H-switch output port, the Q1 packets must appear in the same
order at the output port as they appeared at the input port.
4. When Q1 packets from multiple H-switch input ports are multicasting to
common output ports, the Q1 packets must appear in the same order at all
of the output ports that they target.