Service manual

B-14 AlphaServer GS80/160/320 Service Manual
B.7.3 I/O Space Writes
Figure B– 4 I/O Space Write Transaction Flow Diagram
Source Processor
Issues a reference
to IO address X
IO Processor
IO Device
Source of PIORd Data
or
Destination of PIOWr Data
Arb
QIO PIOWr
Q1 WrIO Comsig
QIO PIOWr
Figure B–4 shows the progress of an I/O space write or programmed IO write
(PIO Wr) transaction through a system. The steps that a transaction may take
in this progression are outlined below.
1. All PIO Wr transactions are issued by a source (or “requesting”) IOP. The
system does not support peer-to-peer I/O transactions.
2. All PIO Wr transactions are sent to the home QBB of the IOP to which they
are targeted in the QIO virtual chanel. The home QBB may be local to the
requesting processor, or it may be another QBB, across the hierarchical
switch.
3. Upon reaching its home QBB, a PIO Wr passes through the QSA quad
switch arbiter (QSA QS Arb). All QIO transactions, including PIO Wr
transactions, arbitrate not for memory or directory banks, but for access to
the command/address interconnect (the ArbBus) between the home QSA
and the home IOP.
4. Upon winning arbitration at the home QS Arb, the PIO Wr generates a Wr
IO Comsig packet back to the requesting processor. The Wr IO Comsig
travels back to the requesting processor as a Response Packet in the Q1
Virtual Channel.