Service manual

Cache Coherency B-13
Figure B–3 shows the progress of an I/O space read or Programmed IO Read
(PIO Rd) transaction through a system. The steps a transaction may take are as
follows:
1. All PIO Rd transactions are issued by a source (or “requesting”) processor.
The source processor in this case must be a CPU, not an IOP.
2. All PIO Rd transactions are sent to the home QBB of the IOP to which they
are targeted in the QIO virtual channel. The home QBB may be local to the
requesting processor, or it may be another QBB, across the hierarchical
switch.
3. Upon reaching its home QBB, a PIO Rd passes through the QSA quad
switch arbiter. All QIO transactions, including PIO Rd transactions,
arbitrate not for memory or directory banks, but for the command/address
interconnect (the ArbBus) between the home QSA and the home IOP.
4. The home IOP module retrieves read data from the device addressed in the
PIO Rd transaction.
5. The home IOP starts a data return sequence by issuing a PIO Rd Response
transaction to the home QSA. This transaction travels in the Q0 virtual
channel.
6. Upon reaching the home QSA, the PIO Rd Response starts two events:
• It spawns a Q2 IO Fill packet, which returns data to the requesting
processor directly (without passing through the home QS Arb).
• It passes itself through the QSA QS arbiter. PIO Rd Response
transactions for access to the Q1 virtual channel.
7. Upon winning arbitration at the home QS Arb, the PIO Read Response
generates a Rd IO Comsig packet. The Rd IO Comsig travels back to the
requesting processor as a Response Packet in the Q1 Virtual Channel.