Service manual

Cache Coherency B-11
3. Upon reaching its home QBB, a memory space transaction arbitrates for
access to a home directory bank and a home memory bank. When the
transaction is granted access to the directory and memory, it accesses both
the cache state and the data stored in the block’s memory location.
When the cache state is accessed, it is combined with the transaction’s
command type to:
• determine, and atomically update, the next coherency state.
• generate a response packet to the requesting processor.
• generate probe packets to processors with Dirty or Shared copies of the
block.
4. The response and probe packets generated by a Q0/Q0Vic transaction at its
home directory travel to the requesting processor and processors with Dirty
and Shared copies on the Q1 Virtual Channel.
5. If an Fwd Read-type probe packet was generated in step #3 and shipped to a
Dirty Processor in step #4, then the Dirty Processor must ship the Dirty data
back to the requesting processor. Dirty data is returned to the requesting
processor in the Q2 Virtual Channel.