Service manual

B-10 AlphaServer GS80/160/320 Service Manual
B.7 Virtual Channels and Coherency Flow
The virtual channels are useful in explaining how transactions flow through the
system while maintaining cache coherency.
B.7.1 Memory Space Transactions
Figure B– 2 Memory Space Transation Flow Diagram
Home Memory
May
hold
X
Source Processor
Issues a reference
to address X
Dirty Processor
If X is dirty, this
processor has the
most up to data
copy of X
Shared Processor
This processor has
a copy of X.
Home Directory
Holds coherency
information
relevant to X
Q0
Q0Vic
Q1
Q1
Response
Packet
Q1
Probe
Packet
(Fwd Rd or Inval)
Q2
Dirty
Data
Q1
Probe
Packet
(Inval)
Figure B–2 illustrates the progression of a memory space transaction through a
system. The steps that a transaction may take in this progression are outlined
below.
1. All memory space transactions (or “requests”) are issued from some source
(or “requesting”) processor, be it a CPU processor or an IOP.
2. All memory space transactions are routed to their home QBB regardless of
the location of the latest copy of the block. The home QBB may local to the
requesting processor, or it may be another QBB, across the hierarchical
switch.
All memory space transactions en route to their home directory travel in
virtual channels Q0 and Q0Vic.