Service manual

Cache Coherency B-7
B.4 Cache State Transition Diagram
Figure B–1 shows how both memory space commands and system probe
commands cause cache block state to change. Circles in the diagram represent
the state of a given cache block. Cache blocks change state as a result of a
particular command affecting the block represented by the arrows.
Figure B– 1 Cache State Transition Diagram
Invalid
Clean
Dirty
Clean/
Shared
Dirty/
Shared
CtoD
Rd
Inval
Evict
StoD
FRd
FRdM or Inval
Evict
Evict
RdM or ItoD
FRdM or Inval
B.5 Commands and Cache State Interaction
Shows how probe commands follow from the interaction of memory space
commands and the state of the target cache block in a cache. The table assumes
that a processor, CPU0, issues a memory space command to the system. If the
target of the command is a cache block located in say CPU1’s cache, as
determined by a tag comparison (either directory of DTAG), then the state of
the cache block determines which probe command will be issued to CPU1.