Service manual

Cache Coherency B-3
B.2 Cache States
The Alpha CPU chip supports five cache states and two sets of commands that
affect them. The AlphaServer GS series uses both command sets and four of the
five cache states. It is the AlphaServer GS series cache coherency scheme that is
described in this section.
The AlphaServer GS series cache states are described in Table B–2.
Table B– 2 AlphaServer GS Series Cache States
Cache State Description
Clean The cache location holds a copy of a memory block. Memory,
or another processor, holds the “most up to date” copy of the
block. A cache block may be clean even though there may be
other copies of the block else where in the system.
Dirty The cache location holds an exclusive, “most up to date” copy
of a memory block and the cache location is writeable. The
data cached at this location must be written back to memory
before this location can be reused.
Dirty - Shared The cache location holds the “most up to date” copy of a
memory block, while another cache holds a copy of the same
memory block. The block was read from the former’s cache
into the latter’s cache after it was modified. The cache
location is no longer write-able and must be written back to
memory before the cache location can be reused.
Invalid Cache location holds no data.