Service manual

B-2 AlphaServer GS80/160/320 Service Manual
B.1 Terminology
Table B–1 shows the definitions of terms related to cache coherency.
Table B–1 Basic Cache Coherency Terminology
Term Definition
Block
A single, contiguous, 64-byte segment of memory, which must
start on a 64-byte aligned memory address
Cache block
A single entry in a processor’s cache memory, equal to one block
of data
Clean
Indicates that the data in a cache block has not been modified by
the processor associated with the cache
Commander
A component (node) in the system that participates in arbitration
and initiates transactions
Dirty
Indicates that the data in a cache block has been modified by the
processor associated with the cache
Responder
A node on the arbitration bus which accepts or supplies data and
status information in response to a command and address from a
commander
Shared
Indicates that the data in a cache block of one processor is also
contained in the cache of another processor in the system
Transaction
A complete operation that results from a command
Victim
Indicates that the data in a cache block of a processor is valid but
is about to be replaced by another block of data from memory