Service manual

System Overview 1-19
Figure 1–9 is a block diagram of a 16-processor GS160 system. It consists of
two full system boxes with two QBBs in each. In this case, only four of the eight
ports in the hierarchical switch (H-switch) are used to pass command/address
and data between nodes.
Since these systems use distributed memory, the hierarchical switch is required
to help maintain systemwide coherency. First, it supports multicasting.
Whenever a processor attempts to gain ownership of a memory block,
“invalidates” may need to be broadcast to the other quad processor switches.
Therefore, certain packets transmitted by a global port will have multiple
destinations. When the H-switch sees multiple destinations, it will “multicast”
the packet to all target ports. The second coherency requirement is that the
hierarchical switch must maintain certain ordering for packets received from
and transmitted to the global ports. For a full description of coherency, see
Appendix B.
Paths in the H-switch are all unidirectional – either transmit or receive – so it
is possible to have 16 transactions passing through the switch simultaneously.
Each of the 8 ports connected to QBB global ports can be transmitting and
receiving data at the same time. It should be noted that transactions are
buffered in many locations throughout the system, in memory, global ports,
directories, CPUs, I/O subsystems, etc., such that a large system could be
keeping track of over 300 transactions at any given time.
When transactions cross QBB boundaries in systems with more than two
QBBs, command/address and data pass through the local global port, through
the H-switch, and through the remote global port to their ultimate destination.