Service manual

System Overview 1-17
Figure 1–8 shows an 8-processor, two QBB system. Such a system can be built
using a rack cabinet and two drawers (a GS80 system) or a system and power
cabinet and a loaded system box (an 8-P GS160 system). This configuration is
the maximum for the rack GS80 system.
The directory contains state information on each 64-byte (cache-block-size)
chunk of main memory in the system. Like memory, the directory is distributed
across system nodes such that if a memory address is located on a particular
node the directory module on that node knows its state, ownership, and current
location of the most up to date copy of the block. The directory makes the
primary memory coherence decisions.
The global port performs two major functions: first to pass command/address
and data between the nodes and second to keep track of transactions that are
not complete. This second function is important in keeping memory coherent.
Since DTag and directory data are typically updated once a transaction is
complete, the Transaction Tracking Table (TTT), a CAM (content addressable
memory) located on the global port, keeps track of incomplete transactions (in
flight transactions) at a given node. Thus, cache blocks accessed by more than
one CPU at the same time can be correctly tracked and updated. For a full
description of coherency, see Appendix B.
In a two QBB system, a global port in QBB0 communicates with a global port in
QBB1 through a distribution board.
In addition to the system functions just described, the console serial bus (CSB)
routes through the global port.
For a description of the global port module, see Section 1.17.