Service manual

System Overview 1-15
Figure 1–7 shows a single QBB. CPUs access memory and I/O through the local
11-port switch. In a four-processor (4-P) system, no communication off the QBB
backplane, other than I/O and system management, is necessary. Therefore,
neither the global port nor the directory modules are needed. Not shown in the
diagram is the console serial bus used for system management. See Section
1.8.1 for information on the console serial bus.
The local switch consists of quad switch address chips and quad switch data
chips. Four bidirectional ports are dedicated to memory, four bidirectional ports
are dedicated to processors, one bidirectional port is connected to the IOP, and
two unidirectional ports, one for transmit and the other for receive, are
connected to the global port. (Note that in GS80 systems the global port is built
into the drawer backplane.)
The duplicate tag store (DTag) maintains a copy of the state of each processor’s
B-cache tags so that the system can access the state of a given piece of data at a
particular address. As one can imagine, keeping track of ownership and state of
memory locations in a system in which memory is physically located in one or
more QBBs is a major system task. The DTag performs its part in that effort by
tracking the ownership and state of data locally.
For a full description of coherency, see Appendix B.