Service manual

Power-Up 2-27
Refer to continuation 3 of Example 2–2.
Phase 2 begins.
The pass/fail results of phase 1 are passed back to the SCM indicated by
the ~I~ line. An I/O map built by the PSM, now the result of remote
testing, is passed to the SCM monitor.
Phase 2 testing is done on each QBB. Phase 2 consists of a single test. The
caches of each secondary CPU are victimized – that is, written back into
memory with the result that memory and caches are now coherent. For
detailed information on cache coherency, see Appendix B.
Again the system map is displayed.
Phase 3 testing is done on each QBB. Phase 3 tests that each CPU can
access each memory in each QBB in the system. See Table 2–5 for a list of
these tests.
A final system map is displayed.
The system primary CPU, in this case CPU0, unloads the console code
from the master PCI box over an identified path.
The secondary CPUs in each QBB start running the console code.
After phase 4 step E (console unload), power-on is complete and control of
the system is passed to COM1. The SCM monitor relinquishes control of
the system and turns control over to the SRM console if the environment
variable AUTO_QUIT_SCM is enabled.