Service manual

Power-Up 2-25
QBB0 now Testing Step-9. |
QBB0 now Testing Step-A. |
QBB0 now Testing Step-7. |
QBB0 now Testing Step-8. |
QBB0 now Testing Step-9.. |
QBB0 now Testing Step-A. |
QBB0 now Testing Step-7. |
QBB0 now Testing Step-8.. |
QBB0 now Testing Step-9. |
QBB0 now Testing Step-A. |
QBB0 now Testing Step-B. |
Refer to continuation 1 of Example 2–2.
Phase 0, local QBB testing begins. See Section 2.2 for information on
testing done in phase 0.
The SCM sends the H-switch a mask of links between the global ports and
the H-switch to enable the links.
The configuration data from the initialization phase is displayed.
The links between the H-switch and the global ports in each QBB are on.
This is the result of the command sent in
.
Phase 0 steps 1 through 5 are run on each QBB. Had any test failed, an
error message would have printed in the display. Phase 0 ends.
If errors had occurred in phase 0, error messages would have appeared
here. Had there been any errors, the configuration described here might be
different from the configuration described in
. See Section 2.7 for
information on interpreting SROM/XSROM error messages. Note that
when diagnostics fail, they may call out several different FRUs. The SCM
monitor may drop from the configuration those resources that the
diagnostic identifies as being the most likely failing unit (FRU1). It will
not drop those resources identified by the diagnostic as FRU2 – FRU4.
Each step of phase 1 is performed on each QBB. In phase 1 a system
primary CPU is chosen and it tests each QBB over a path out its global
port through the hierarchical switch and in to the QBB under test through
its global port. For a list of tests run in phase 1, see Table 2–4.