Service manual

Power-Up 2-23
Example 2–2 shows a continuation of the SCM console display after the OCP
switch has been put in the On position.
Refer to Example 2–2.
PCIs and QBBs are powered on.
The QBBs are powered on and the Init. Phase is started.
The SROM code (step 0) is run on each CPU in each QBB.
The master SCM is SCM_E0 and, in this case, the slave SCM is SCMe1.
The message displayed here indicates that while the slave SCM is testing
its shared RAM, the master SCM recognizes that fact. The standard I/O
shared RAM is tested and initialized. The SCM, SRM console, and
operating systems use this RAM to pass information to each other.
The PSM in each QBB is told to establish the relationship between
transmit and receive time between each element (CPU, memory, global
port, and directory) attached to the local quad switch. In other words, the
local switch is started and synchronized.
The standard I/O shared RAM is tested and initialized. The SCM, SRM
console, and operating systems use this RAM to pass information to each
other.
HPM is told to establish the relationship between transmit and receive
time between each element (global ports) attached to the hierarchical
switch. In other words, the hierarchical switch is started and
synchronized.