Service manual

Power-Up 2-17
The phase 2 test “victimizes” all cache blocks of all secondary CPUs. (The SP CPU
“victimized” all its cache blocks at the end of phase 1.) A victimized cache block is one
that the CPU has modified and wishes to write back to memory. Writing data back to
memory assures that the contents of B-cache, DTags, and memory are coherent.
The phase 3 tests assure that each CPU interacts correctly with its own B-cache and the
QBB’s DTag and can access each memory array in the entire system. In an eight QBB
system each with four fully loaded memory carriers produces a maximum of 64 memory
arrays to test by each CPU in the system. The memory access test operates on only one
cache block in each array.
During phase 4, the SP CPU unloads the PAL/console code from the flash ROM on the
standard I/O module into memory. It then places the starting address of the code in
memory in its QSD CPUx scratch register. The secondary CPUs read that register
waiting for the address and when it arrives, jump to the address and start running
console code. All CPUs now run PAL/console code.
The SRM console conducts the rest of power-up.
Table 2–5 lists the XSROM tests run during phases 2, 3, and 4.
Table 2– 5 XSROM Tests Run in Phases 2, 3, and 4
Test # Test Name
Phase 2 Step C test
53 Secondary cache victimization test
Phase 3 Step D tests
54 B-cache TAG data line testing (run by all CPUs)
55 Memory access test (run by all CPUs)
56 Low memory mailbox access test (run by all CPUs)
57 Memory thrashing test (run by all CPUs)
Phase 4 Step E tests
58 Console flash ROM checksum and unload test (CSB)
59 Console (alternate) flash ROM checksum and unload test (CSB)
Phase 4 Step F tests
5a – 5c
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5d CPU hot-swap cache victimization/jump to console test
5e – 5f
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