Service manual

Power-Up 2-7
Power-up consists of an initialization phase followed by five test phases. The
system control manager (SCM) firmware, run by the microprocessor on the
standard I/O module, controls power-up. The SCM, master of the console serial
bus (CSB), sends power-up control test packets over the CSB to the PSMs in
each QBB. The PSMs in turn pass power-up control test packets to the CPUs in
the QBBs over the PSM to CPU serial lines.
Each microprocessor on the CSB (SCM, PSM, PBM, and HPM) has both an
application image and a fail-safe loader (FSL) image in flash ROM.
When power is applied (or a reset is initiated), each microprocessor runs its FSL
image that performs a checksum on the application image. If the checksum is
bad, the microprocessor remains in FSL mode and the particular resource it
controls will not be configured into the system. If the SCM fails the checksum,
the system will not power up. Appropriate messages appear at the console. See
Section 3.10 for more on the FSL.
A phase is executed during the time between communication points established
between the SCM and PSMs. Steps within phases are tests executed between
communication points between the PSM and SROM/XSROM code running on
the CPU(s).
During the initialization phase, SROM code is loaded into I-cache of each CPU
in the system and communication between the PSM and CPU is established
over the serial lines. No tests are conducted.
During phase 0, “local” testing of each QBB in the system is conducted. No
testing is conducted between QBBs if more than one is present. At the end of
phase 0, in addition to knowing the location of standard I/O module(s), the
following is known about each QBB:
• Whether self-test passed or failed on CPUs, PSMs, DTags, DIRs, IOPs, and
memory
• Whether the QBB switch, the global port, and the I/O path to the PCAs
work
• The state and size of directory memory if it is working
• The state and size of the DTag if it is working
• Nothing about QBBs without CPUs other than the fact that they exist
Table 2–2 and Table 2–3 list the SROM tests and XSROM tests run during
phase 0.