Specifications

9 March 1999 – Subject To Change System Address Space A–29
PCI Configuration Space
Note: If a quadword access is specified for the configuration cycle, then the
least significant bit of the register number field (such as ad<2>) must be
zero. Quadword transactions must access quadword aligned registers.
If the PCI cycle is a configuration read or write cycle but the ad<1:0> are 01 (that is,
a type 1 transfer), then a device on a hierarchical bus is being selected via a PCI-to-
PCI bridge. This cycle is accepted by the PCI-to-PCI bridge for propagation to its
secondary PCI bus. During this cycle, <23:16> selects a unique bus number, and
address <15:8> selects a device on that bus (typically decoded by the PCI-to-PCI
bridge to generate the secondary PCI address pattern for IDSEL). In addition,
address <7:2> selects a Dword (longword) in the device’s configuration space.
Table A–10 contains the PCI configuration space read/write encodings.
Each PCI-to-PCI bridge can be configured via PCI configuration cycles on its primary
PCI interface. Configuration parameters in the PCI-to-PCI bridge will identify the bus
number for its secondary PCI interface and a range of bus numbers that may exist hier-
Table A–10 PCI Configuration Space Read/Write Encodings
Size Byte Offset
addr_h
<6:5>
21164
Instruction
Allowed ad<2:0>
PCI Byte
Enable
1
1
Byte enable set to 0 indicates that byte lane carries meaningful data.
Data-In Register
Byte Lanes
63.....32 31.......0addr_h<4:3>
00 A<7>
2
,00
2
A<7> = addr_h<7>.
1110 OOOX
01 A<7>,00 1101 OOXO
Byte 00 10 LDL,STL A<7>,00 1011 OXOO
11 A<7>,00 0111 XOOO
00 A<7>,00 1100 OOXX
Word
3
3
Missing entries (for example, word size with addr_h<6:5> = 11) generate UNPREDICTABLE results.
01 01 LDL,STL A<7>,00 1001 OXXO
10 A<7>,00 0011 XXOO
00 A<7>,00 1000 OXXX
Tribyte 10 01 LDL,STL A<7>,00 0001 XXXO
Longword 11 00 LDL,STL A<7>,00 0000 XXXX
Quadword 11 11 LDQ,STQ 000 0000 XXXX XXXX