Specifications

A–20 System Address Space 9 March 1999 – Subject To Change
PCI Sparse Memory Space
Table A–6 defines the low-order PCI sparse memory address bits. Signals
addr_h<7:3> are used to generate the length of the PCI transaction in bytes, the byte
enable bits, and ad<2:0>. The 21164 signals addr_h<30:8> correspond to the quad-
word PCI address and are sent out on ad<25:3>.
Table A–6 PCI Memory Sparse-Space Read/Write Encodings
Size Byte Offset
addr_h
<6:5>
21164
Instruction
Allowed ad<2:0>
PCI Byte
Enable
1
1
Byte enable set to 0 indicates that byte lane carries meaningful data.
Data-In Register
Byte Lanes
63.....32 31.......0addr_h<4:3>
00 A<7>
2
,00
3
2
A<7> = addr_h<7>.
3
In PCI sparse memory space, ad<1:0> is always zero.
1110 OOOX
01 A<7>,00 1101 OOXO
Byte 00 10 LDL,STL A<7>,00 1011 OXOO
11 A<7>,00 0111 XOOO
00 A<7>,00 1100 OOXX
Word
4
4
Missing entries (for example, word size with 21164 address = 11) enjoy UNPREDICTABLE results.
01 01 LDL,STL A<7>,00 1001 OXXO
10 A<7>,00 0011 XXOO
00 A<7>,00 1000 OXXX
Tribyte 10 01 LDL,STL A<7>,00 0001 XXXO
Longword 11 00 LDL,STL A<7>,00 0000 XXXX
Quadword 11 11 LDQ,STQ 000 0000 XXXX XXXX