Specifications

9 March 1999 – Subject To Change System Address Space A–19
PCI Sparse Memory Space
• Hardware does not perform read-ahead (prefetch) transactions in sparse space
because read-ahead transactions may have detrimental side effects.
• Programmers are required to insert memory barrier (MB) instructions between
sparse-space transactions to prevent collapsing in the 21164 write buffer. How-
ever, this is not always necessary. For example, consecutive sparse-space
addresses will be separated by 32 bytes (and will not be collapsed by the 21164).
• Programmers are required to insert MB instructions if the sparse-space address
ordering/coherency to a dense-space address is to be maintained.
• Table A–6 shows encoding of the 21164 address for sparse-space read transac-
tions to PCI space. An important point to note is that signals addr_h<33:5> are
directly available from the 21164 pins. On read transactions, the 21164 sends out
addr_h<2:0> indirectly on the int4_valid pins. Signals addr_h<2:0> are
required to be zero. Transactions with addr_h<2:0> not equal to zero will pro-
duce UNPREDICTABLE results.
• Table A–5 shows the relation between int4_valid<3:0> and addr_h<4:3> for a
sparse-space write transaction. Unlisted int4_valid patterns will produce
UNPREDICTABLE results (that is, as a result of collapsing in the 21164 write
buffer; or by issuing a STQ instruction when a STL instruction is required).
Table A–5 Int4_valid and 21164 Address Relationship
EV5 Data Cycle Int4_valid<3:0>
1
1
All other int4_valid patterns result in UNPREDICTABLE results.
Address<4:3>
First 00 01 0 0
00 10 0 0
01 00 0 1
10 00 0 1
Second 00 01 1 0
00 10 1 0
01 00 1 1
10 00 1 1
11 00 (STQ)
2
2
Only one valid STQ case is allowed.
1 1