Specifications

4–16 Functional Description 9 March 1999 – Subject To Change
Reset and Initialization
At system reset, the 21164 microprocessor’s irq_h<3:0> pins are driven by the clock
divisor values set by four jumpers on J27. During normal operation, these signals are
used for interrupt requests. The pins are either switched to ground or pulled up in a
specific combination to set the 21164 microprocessor’s internal divider.
The 21164 microprocessor produces the divided clock output signal sys_clk_out1
that drives the CY2308 PLL clock-driver chip. This clock provides the references to
synchronize the 21164 microprocessor and the 21174 chip. The 21174 provides the
system memory and I/O (PCI) clock references. It also provides system-level clock-
ing to DIMMs, PCI slots, the PCI-ISA bridge, the PCI ID controller, and the PCI
arbiter.
A 14.3-MHz crystal produces the signal 14mhz_out. This signal is delivered to the
37C935 combination controller for the diskette data separator and other I/O clocks.
The combination controller produces output clock osc, which is then delivered to the
two ISA slots and the PCI-to-ISA bridge for synchronization.
4.6 Reset and Initialization
A TL7702B power monitor senses the +3.3-V rail to ensure that it is stable before
+2.5 V is applied to the 21164 microprocessor. In normal operation, should the
+3.3-V rail fall below 2.5 V, the power monitor enables shdn_l, which turns off the
+2.5-V regulator (pc164lx.32).
An external reset switch can be connected to J21 (pc164lx.28). The reset function
initializes the 21164 microprocessor and the system logic. The p_dcok signal pro-
vides a full system initialization, equivalent to a power-down and power-up cycle.
In addition, the fan sense signal (fan_ok_l) is logically ORed with the reset switch
output and, when enabled, drives rst_l, indicating a fan failure.
The rst_l signal is buffered and drives a set of sys_reset signals to reset the remain-
der of the system, including PCI and ISA devices through the 21174 chip.
Figure 4–8 shows the system reset and initialization logic.