Specifications

9 March 1999 – Subject To Change Functional Description 4–13
Interrupts
4.4.1 Interrupt PLD Function
The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses 804,
805, and 806. This is accomplished by a decode of the three ISA address bits
sa<2:0> and the three ecas_addr<2:0> bits.
Each interrupt can be individually masked by setting the appropriate bit in the mask
register (see Figure 4–6). An interrupt is disabled by writing a 1 to the desired posi-
tion in the mask register. An interrupt is enabled by writing a 0. For example, bit <1>
set in interrupt mask register 1 indicates that the INTB2 interrupt is disabled. There
are three mask registers located at ISA addresses 804, 805, and 806.
An I/O read transaction at ISA addresses 804, 805, and 806 returns the state of the 18
PCI interrupts rather than the state of the masked interrupts. On read transactions, a 1
means that the interrupt source has asserted its interrupt. The mask register can be
updated by writing addresses 804, 805, or 806. The mask register is write-only.
IRQ9 Available
IRQ10 Available
IRQ11 Available
IRQ12 Mouse
IRQ13 Available
IRQ14 IDE
IRQ15 IDE
1
The # symbol indicates an active low signal.
Table 4–3 ISA Interrupts (Continued)
Interrupt
Number Interrupt Source