Specifications

A–46 System Address Space 9 March 1999 – Subject To Change
Suggested Use of a PCI Window
This mem_cs_l range in Figure A–23 is subdivided into several portions (such as the
BIOS areas) that are individually enabled/disabled using CSRs as listed here:
• The MCSTOM (top of memory) register has a 2MB granularity and can be pro-
grammed to select the regions from lMB up to 512MB.
• The MCSTOH (top of hole) and MCSBOH (bottom of hole) registers define a mem-
ory hole region where mem_cs_l is not selected. The granularity of the hole is 64KB.
• The MARl,2,3 registers enable various BIOS regions.
• The MCSCON (control) register enables the mem_cs_l decode logic, and in
addition selects a number of regions (0KB to 512KB).
• The VGA memory hole region never asserts mem_cs_l.
Figure A–23 mem_cs_l Decode Area
Note:
For more detail, please refer to the Intel 82378 System I/O Manual.
4GB
512MB Max
16MB
Main Memory Hole
1MB
1MB-64KB
VGA Memory
(A0000-BFFF)
512KB
MCSTOM
MCSTOH
MCSBOH
MCSCON
MAR1,2,3
MCSCON
MCSCON
LJ-04279.AI4
BIOS Area
Hole
Hole