QuickSpecs
1.
2.
Desired Memory
Desired MemoryDesired Memory
Desired Memory
per Cell
per Cellper Cell
per Cell
(GBs)
Number of DIMMs
Number of DIMMsNumber of DIMMs
Number of DIMMs
Quad Echelon
Quad EchelonQuad Echelon
Quad Echelon
1 GB
1 GB1 GB
1 GB 2 GB
2 GB2 GB
2 GB 4 GB
4 GB4 GB
4 GB
2
22
2 1
11
1 3
33
3 0
00
0 2
22
2 1
11
1 3
33
3 0
00
0
OA, OB
OA, OBOA, OB
OA, OB
1A, 1B
1A, 1B1A, 1B
1A, 1B 2A, 2B
2A, 2B2A, 2B
2A, 2B 3A, 3B
3A, 3B3A, 3B
3A, 3B 4A, 4B
4A, 4B4A, 4B
4A, 4B 5A, 5B
5A, 5B5A, 5B
5A, 5B 6A, 6B
6A, 6B6A, 6B
6A, 6B 7A, 7B
7A, 7B7A, 7B
7A, 7B
2 2
1 GB
1 GB1 GB
1 GB
4 4
1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB
8 6
1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB
16 16
1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB
24
8 8
2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB 1 GB
1 GB1 GB
1 GB
32
16
2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB
48
8 8
4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB 2 GB
2 GB2 GB
2 GB
64
16
4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB 4 GB
4 GB4 GB
4 GB
Performance Tuning
Performance TuningPerformance Tuning
Performance Tuning
Guidelines
GuidelinesGuidelines
Guidelines
For best performance, a cell should be configured with a multiple of 8 DIMMs or four pairs
(although the server will execute properly with an odd number of pairs). It takes 8 DIMMs to
populate both memory buses. Populating only one of the two memory buses on a cell board will
deliver only half the peak memory bandwidth.
Load memory equally across the available cell boards.
Memory Latencies
Memory LatenciesMemory Latencies
Memory Latencies
There are two types of memory latencies within the HP Integrity rx8640 Server:
Memory latency within the cell refers to the case where an application either runs on a partition
that consists of a single cell or uses cell local memory.
Memory latency between cell refers to the case where the partition consists of two or more cell and
cell interleaved memory is used. For example, for an rx8640 server with four cells in the partition,
25% of the addresses are to memory on the same cell as the requesting processor, and the other
75% of the addresses are to memory on the other three cells.
The HP Integrity rx8640 Server memory latency depends on the number of processors in the partition.
Assuming that memory accesses are equally distributed across all cell boards and memory controllers
within the partition, the average idle memory latency (load to use) is as shown below:
Number of processors
Number of processorsNumber of processors
Number of processors
Average Memory Latency
Average Memory LatencyAverage Memory Latency
Average Memory Latency
4-processor
185 ns
8-processor
249 ns
16-processor
334 ns
QuickSpecs
HP Integrity rx8640 Server
HP Integrity rx8640 ServerHP Integrity rx8640 Server
HP Integrity rx8640 Server
Configuration
DA - 12471 Worldwide — Version 14 — November 8, 2007
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