User's Manual

COMPANY CONFIDENTIAL
Preliminary Datasheet
11
4.2 Pin definition
Pin No.
Pin Name
Type
Description
Voltage
Conne
cting
1-3, 7-16,
18,19,21,
22,25,
43-44,66,
67
NC
-
No connection
-
No
4,5,72,73
3.3V
Power
DC 3.3V power input
3.3V
Yes
24
BT_DEV_WAKE
I
Bluetooth device wake-up: Signal from the
host to the BCM4356 indicating that the host
requires attention.
• Asserted: The Bluetooth device must
wake-up or remain
awake.
• Deasserted: The Bluetooth device may
sleep when sleep criteria are met. The
polarity of this signal is software
configurable and can be asserted high or
low.
1.8V
Yes
27
SUSCLK (32KHz)
I
Suspend Clock is a 32.768 kHz clock supply
input that is provided by platform to enable
the add-in card to enter reduce power
consumption modes. SUSCLK will have a
duty cycle that can be as low as 30% or as
high as 70%. Accuracy will be up to
200ppm. See the detail spec in section6.
1.8V
(Note1)
Yes
28
WLAN_RFDISAB
LE_L
I
Active low, debounced signal when applied
by the system it will disable WLAN radio
operation on the add-in cards that implement
radio frequency applications. This signal is
internal pull-up on the card by default.
1.8V
(Note2)
No
29
PCIE_PME_L
OD
PCIe PME Wake. Open Drain with pull up on
platform; Active Low
1.8V
Yes
30
PCIE_CLKREQ_
L
OD
Clock Request is a reference clock request
signal as defined by the PCIe Mini Card CEM
specification; Also used by L1 PM Substates.
1.8V
Yes
31
PCIE_PERST_L
I
PE-Reset is a functional reset to the Add-In
card as defined by the PCIe Mini Card CEM
specification
1.8V
Yes
33
PCIE_REFCLKN
I
PCIe Reference Clock signals (100 MHz)
defined by the PCIe2.0 specification.
-
Yes
34
PCIE_REFCLKP
36
PCIE_TDN
O
PCIe TX differential signals defined by the
PCIe2.0 specification
-
Yes
37
PCIE_TDP
39
PCIE_RDN
I
PCIe RX differential signals defined by the
PCIe2.0 specification. Add AC cap 0.1uF on
PCIe signals of host side.
-
Yes
40
PCIE_RDP
42
VIO
Power
Reserved for external 1.8V power source
input. If don’t need, MUST keep it floating or
open
1.8V
(Note3)
Option
45
WL_REG_ON
I
SDIO sideband GPIO pin to enable/disable
(reset) the WiFi function. Platform firmware is
required to assert/de-assert this pin on every
boot (warm and cold). High active. See the
detail sequence timing in section5.3.
1.8V
Yes
46
SDIO_WAKE_L
O
SDIO Host Wake. Note in band SDIO wake is
not used for non-active modes, Active Low.
Require pull up on the host side
( recommended 15K to 100K )
1.8V
No