User's Manual

2-6. Peripherals
The general GPIO is organized as one port with up to 30 I/Os enabling access and control of up to 30 pins through one
port. Each GPIO can be accessed individually with the following user configurable features.
Input/output direction
Output drive strength
Internal pull-up and pull-down resistors
Wake-up from high or low level triggers on all pins
Trigger interrupt on all pins
All pins can be used by the PPI task/event system.
The maximum number of pins that can be interfaced through the PPI at the same time is limited by the number of GPIOTE
channels
All pins can be individually configured to carry serial interface or quadrature demodulator signal.
The transceiver receives and transmits data directly to and from system memory for flexible and efficient packet data
management. The module’s transceiver has the following features.
General modulation features
GFSK modulation
Data whitening
On-air data rates (250 kbps/1 Mbps/2 Mbps)
Transmitter with programmable output power of +4 dBm to -20 dBm, in 4 dB step
RSSI function (1 dB resolution)
Receiver with integrated channel filters achieving maximum sensitivity
Baseband controller
Easy DMA RX and TX packet transfer directly to and from RAM
Dynamic payload length
On-the-fly packet assembly/disassembly and AES CCM payload encryption
8 bit, 16 bit and 24 bit CRC check
The timer runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X)
pre-scaler that can divide the timer input clock from the HFCLK controller. Clock source selection between PCLK16M and
PCLK1M is automatic according to TIMER base frequency set by the pre-scaler.
The TIMER base frequency is always given as 16 MHz divided by the pre-scaler value.
The PPI system allows a TIMER event to trigger a task of any other system peripheral
of the device. The PPI system also enables the TIMER task/event features to generate periodic
output and PWM signals to any GPIO. The number of input/outputs used at the same time
is limited by the number of GPIOTE channels.