Service manual

The Clock Circuits
Crystal Y1 outputs a 16Mhz clock signal. THis is input to UD5 on pin 8. UD5 is configured as a ÷ 16
frequency divider. The output of UD5 pin 12 is a 1 MHz clock signal used as the system clock (Phase
0) for the microprocessor. UE6 is a programmable counter ( ÷ 16, ÷ 15, ÷ 14, ÷ 13) that outputs a
varying frequency clock used to compensate for the difference in recording area/sector for sectors on
inner tracks (Trks 1,2,3) as compared to sectors on out most tracks (Trks 33,34,35). The area/sector
for inner tracks is less than the area/sector for out most tracks, so the recording clock frequency is
increased when writing on inner tracks to keep the flux density constant. This clock output is on pin
12 of UE6.
Tracks
Clock Frequency
Divide By
1-17
1.2307
MHz
13
18-24
1.1428
MHz
14
15-30
1.0666
MHz
15
31-35
1
MHz
16