System information

17-Nov-2014 G2T Programmers Guide Rev-A

• The ESR contains several bits which in practice indicate the

success or failure of a command to execute and respond.

It is set by the various conditions and read by the *ESR?

Command. Reading it clears it.

• The ESER is “and’ed” with the ESR to generate the SBR’s ESB

bit. It is written with the *ESE command and can be read

with the *ESE? Command.

• Set CME, EXE or QYE bits in the ESR indicate that an error

code is stored in LCE, LEE or LQE. These are read by GET?

Xx.

The device maintains a separate set of registers for each interface

(assuming there’s more than one). In practical terms, this means

that each interface can have, for example, a separate SRER or

ESER. The Fault Queue, on the other hand, is common to all

interfaces in the device.

Several conditions ultimately determine the current value of MSS.

For example, setting the OPC bit of the ESR does not necessarily

set MSS. First OPC’s bit in the ESER must be set in order for ESB to be

set, then ESB’s bit in the SRER must be set before the condition

exists to set MSS.

As each change occurs, the value of MSS is re-evaluated and

updated regardless of whether the change was an internal

condition or a commanded change of one of the enable

registers. On GPIB interfaces, as MSS is set or cleared, the need to

request service or cancel a previous service request is also

evaluated.