User guide

CIF Peripheral Model - SimpleTimer
84 CoMET Version 5.9 – Tutorial
Timer Interrupt Enable Register (TIER)
The Timer Interrupt Enable Register (TIER) is a 2-bit register, one bit per special timer: ‘1’
enables the timer interrupt, and ‘0’ disables the timer interrupt. Note that the address is
word-aligned and can be read as a byte or a word, but only the two bits are used.
 Register is readable and writeable
 Value after reset = 0x00000000;
3. Address offset: 0x10;
Timer Interrupt Flag Register (TIFR)
The Timer Interrupt Flag Register (TIFR) is a 2-bit register, one bit per special timer. A bit is
set to ‘1’ if its corresponding timer generates an interrupt. This register is a read-modify-write
register. Write a 0 to the particular bit to clear the interrupt. Note that the address is word-
aligned and can be accessed as a byte or a word, but only Bits 0 and 1 are used.
 Register is readable and writeable
 Value after reset = 0x00000000;
 Address offset: 0x18;
Bit
31
Bit
30
Bit
29
Bit
28
Bit
27
Bit
26
Bit
25
Bit
24
Bit
23
Bit
22
Bit
21
Bit
20
Bit
19
Bit
18
Bit
17
Bit
16
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
MSB
LSB
Unused
Unused
TIER1
TIER2