User guide

CIF Peripheral Model - SimpleTimer

CoMET Version 5.9 – Tutorial 83

Timer Enable Register (TER)

The Timer Enable Register (TER) is a 2-bit register, one bit per special timer: ‘1’ enables the

timer, and ‘0’ disables the timer. Note that the address is word-aligned and can be read as a

byte or a word, but only the two bits are used.

 Register is readable and writeable

 Value after reset = 0x00000000;

 Address offset: 0x08;

Bit

MSB

LSB

Upper 16 bits of the match value

Lower 16 bits of the match value

Bit

MSB

LSB

Unused

TER2

TER1