User guide

CIF Peripheral Model - SimpleTimer

82 CoMET Version 5.9 – Tutorial

Registers

The SimpleTimer requires registers to enable and configure the timer, as well as provide a

mechanism for the embedded target software to communicate with the device. The timer has

the following registers:

General Timer Register (GTR)

The General Timer (GT) is the reference timer used by the Match Timers. It consists of a 32-

bit counter register called the General Timer Register (GTR). The CPU can directly read or

write the GTR, but only as an entire word (4-byte value).

 Register is readable and writeable

 Value after reset = 0x00000000;

 Address offset: 0x00;

Match Timer Registers (MTR1 and MTR2)

Each Match Timer Register is a 32-bit compare timer, which generates an interrupt when the

Match Timer Register value is equal to the General Timer Register value, if the

corresponding Timer Enable Register (TER) and Timer Interrupt Enable Register (TIER) bit

is set. The Match time is equal to the MTR value multiplied by the timer clock period.

The CPU can directly read and write MTR1 and MTR2, but only as entire words (4-byte

values).

 Registers are readable and writeable

 Value after reset = 0x00000000;

 Address offset: MTR1: 0x28, MTR2: 0x30;

Bit

MSB

LSB

Upper 16 bits of the free running counter value

Lower 16 bits of the free running counter value