User guide

CIF Peripheral Model - SimpleTimer
CoMET Version 5.9 – Tutorial 113
#ifdef _DEBUG
AmpiStreamPrintf(DEBUG_MSG, "%s: Write data %#06x to
TIER\n",IP->pModulePathName,Data);
#endif
if (IP->regTIER != (Data & TIER_ENABLE_ALL))
{
IP->regTIER = Data & TIER_ENABLE_ALL;
// Clear the match interrupts that are now disabled.
ClearMatchInterrupts(IP, ~Data);
// Reschedule the next match events.
SetupNextMatch(IP, -1);
}
break;
case TIFR_OFFSET: // Timer Interrupt Flag Register
#ifdef _DEBUG
AmpiStreamPrintf(DEBUG_MSG, "%s: Write data %#06x to
TIFR\n",IP->pModulePathName,Data);
#endif
if ((IP->regTIFR & Data & TIFR_SET_ALL) != IP->regTIFR)
{
IP->regTIFR &= Data & TIFR_SET_ALL;
// Clear the match interrupts that are now turned off.
ClearMatchInterrupts(IP, ~Data);
// Reschedule the next match events.
SetupNextMatch(IP, -1);
}
break;
case MTR1_OFFSET: // Match Timer 1 Register
#ifdef _DEBUG
AmpiStreamPrintf(DEBUG_MSG, "%s: Write data %#06x to
MTR1\n",IP->pModulePathName,Data);
#endif
if (IP->regMTR[MATCH1_IX] != Data)
{
IP->regMTR[MATCH1_IX] = Data;
// Reschedule the next match events.
SetupNextMatch(IP, MATCH1_IX);
}
break;
case MTR2_OFFSET: // Match Timer 2 Register
#ifdef _DEBUG
AmpiStreamPrintf(DEBUG_MSG, "%s: Write data %#06x to
MTR2\n",IP->pModulePathName,Data);
#endif
if (IP->regMTR[MATCH2_IX] != Data)
{
IP->regMTR[MATCH2_IX] = Data;
// Reschedule the next match events.
SetupNextMatch(IP, MATCH2_IX);
}
break;
default:
AmpiStreamPrintf(WARNING_MSG, "%s: Attempt to write to an undefined
register location 0x%lX\n", IP->pModulePathName, Address);
break;
}