User`s guide

Hardware Interrupts
4-12
You need to enter only the name of the ISR that is called in response to a
hardware interrupt in the Property Page of the corresponding HWI object in
the Configuration Tool. DSP/BIOS takes care of setting up the interrupt table
so that each hardware interrupt is handled by the appropriate ISR. The
Configuration Tool also allows you to select the memory segment where the
interrupt table is located.
The online help in the Configuration Tool describes HWI objects and their
parameters. See HWI Module in the TMS320 DSP/BIOS API Reference
Guide for your platform for reference information on the HWI module API
calls.
4.2.2 Disabling and Enabling Hardware Interrupts
Within a software interrupt or task, you can temporarily disable hardware
interrupts during a critical section of processing. The HWI_disable and
HWI_enable/HWI_restore functions are used in pairs to disable and enable
interrupts.
When you call HWI_disable, interrupts are globally disabled in your
application. On the C6000 platform, HWI_disable clears the GIE bit in the
control status register (CSR). On the C5000 and C2800 platforms,
HWI_disable sets the INTM bit in the ST1 register. On both platforms, this
prevents the CPU from taking any maskable hardware interrupt. Hardware
interrupts, therefore, operate on a global basis, affecting all interrupts, as
opposed to affecting individual bits in the interrupt enable register. To
reenable interrupts, call HWI_enable or HWI_restore. HWI_enable always
enables the GIE bit on the C6000 platform or clears the INTM bit in the ST1
register on the C5000 and C2800 platforms, while HWI_restore restores the
value to the state that existed before HWI_disable was called.
4.2.3 Impact of Real-Time Mode Emulation on DSP/BIOS
TI Emulation supports two debug execution control modes:
Stop mode
Real-time mode
Stop mode provides complete control of program execution, allowing for
disabling of all interrupts. Real-time mode allows time-critical interrupt service
routines to be performed while execution of other code is halted. Both
execution modes can suspend program execution at break events, such as
occurrences of software breakpoint instructions or specified program space
or data-space accesses.