User manual
Code Mercenaries
4
LL
LL
EE
EE
DD
DD
--
--
WW
WW
aa
aa
rr
rr
rr
rr
ii
ii
oo
oo
rr
rr
00
00
44
44
This command resets the LW04 to the same status
as a power up does, it can not be combined with
any write commands.
5.1.11 Register 15: Sequence Table Writing
Sequence mode allows the LED-Warrior04 to
autonomously perform dynamic lighting scenarios.
This can be used to generate a power on fading,
continous changing light situations, flashing, color
changing, or any other lighting applications where
a dynamic lighting without a external controller
driving it is required.
Sequence mode is controlled by a table containing
time and PWM values. The table is specified in
5.2.
Before writing to register 15 it has to be enabled by
setting bit 5 of register 12 to "1". The write bit is
automatically reset when the table has been written
completely or an error condition occured.
Each write transaction to register 15 can contain 1
to 9 data bytes. Write transactions automatically go
to ascending table positions until an error condition
is detected, or the table is complete.
Reading from register 15 returns a two byte status
for the sequence table. If the table has been written
successfully the first byte contains the number of
bytes written and the second holds a checksum
generated by xoring all table bytes.
In case of an error the first byte is set to zero and
the second byte contains the error code:
$00 -
$01 - Write bit has been reset before a complete
table header was transmitted
$02 - Write bit has been reset before a complete
table (number of data sets according to table
header) was transmitted
$04 - More data sets than specified in the table
header have been written
$08 - Write access to other registers terminated the
table writing
$10 - Write attempt to register 15 without write
enable bit being set.
$20 - Length data in table header specify too many
data sets (>81).
5.1.12 Broadcast Commands
LED-Warrior04 implements three I2C broadcast
commands. Broadcast comamnds are write only
and are send to address 0.
$04 followed by one data byte sets the I2C address
of the LED-Wariror04 to the data byte as the new
I2C address, values 1…127 are valid.
$0A triggers the activation of new brightness
values for all LED-Warrior04 in sync mode (set in
register 11).
$0B followed by one data byte sets the dimming
source on all connected LED-Warrior04
simulatneously. This is useful to synchronously
start sequence mode on several LED-Warrior04.
The data byte has only two active bits:
Bit 0 - unused, write 0
Bit 1 - unused, write 0
Bit 2 - unused, write 0
Bit 3 - unused, write 0
Bit 4 - Dimming source 0
Bit 5 - Dimming source 1
Bit 6 - unused, write 0
Bit 7 - unused, write 0
Dimming source selects which bus is active or if an
autonomous sequence controls the channels:
0b00 - I2C
0b01 - DMX512
0b10 - DALI
0b11 - Sequence Mode
5.2 Sequence Mode Control
If sequence mode is enabled as the active dimming
source and a valid sequence table has been loaded
LED-Warrior04 will work autonomously executing
the sequence table.
The sequence table is made up of the table header
and up to 81 data sets.
The table header contains the following 10 bytes:
Byte 0 - Sync 0/1
Byte 1 - Sync 2/3
Byte 2 - Repeat 0
Byte 3 - Repeat 1
Byte 4 - Repeat 2
Byte 5 - Repeat 3
Byte 6 - Length 0
Byte 7 - Length 1
Byte 8 - Length 2
Byte 9 - Length 3
Sync contains the flags for each channel to
synchronize with other channels. Sync 0/1 contains
the sync bits for channel 0 in the lower half byte
and for channel 1 in the upper half byte. Sync 2/3
contains the sync bits for channels 2 and 3.
If a sync bit is set the channel waits for the
corresponding channel to come to the end of its
sequence instance before it continues with the next
iteration of its own sequence.
I.e. if Sync0/1 is $04 then channel 0 will wait for
channel 2 to reach the end of its sequence iteration
before it starts its own next iteration. If channel 2
had already reached its sequence iteration end then
channel 0 will continue immediately. Setting
Sync0/1 to $12 will cause channels 0 and 1 to wait
V0.8.0 June 15th 2015 Draft