User Manual
Table Of Contents
- 1GENERAL
- 1.1Introduction
- 1.2Interim Operation
- 1.3Manual Organization
- 1.4UT-4R400 Transmitter Family Models
- 1.5Performance Specifications
- 1.5.1General
- 1.5.2Audio Specifications
- 1.5.3Physical Specifications
- 2THEORY OF OPERATION
- 2.1General
- 2.2Power Supply
- 2.3High Speed Serial Interconnect
- 2.4Audio Circuits
- 2.5PTT Circuitry
- 2.6Microprocessor Board
- 2.7Channel and Bank Selection
- 2.7.1Channel Select Line Mapping
- 2.8Jumper Functions and standard configuration
- 2.9Hang Timer Selection
- 2.10Kerchunk noise selection
- 2.11Test Points
- 2.12Connector Pinouts
- 2.12.1Connector J9
- 2.12.2Connector P1
- 2.13Transmitter Programming
- 2.13.1Transmitter Wide Options
- 2.13.1.1Frequency Band
- 2.13.1.2Source ID
- 2.13.1.3Secure Hardware Equipped
- 2.13.1.4Timeout Options
- 2.13.2Channel Wide Settings
- 2.13.2.1Channel Name
- 2.13.2.2Frequency
- 2.13.2.3Analog Bandwidth
- 2.13.2.4Deviation
- 2.13.2.5Channel Type
- 2.13.2.6Audio Pre-emphasis
- 2.13.2.7Timeout Value
- 2.13.2.8Project 25 Squelch Settings: Network Access Code (NAC)
- 2.13.2.9Project 25 Squelch Settings: Talk Group ID (TGID)
- 2.13.2.10Analog Signaling Settings: Signaling
- 2.13.2.11Analog Signaling Settings: CTCSS Tone
- 2.13.2.12Analog Signaling Settings: Reverse Burst
- 2.13.2.13Analog Signaling Settings: DCS Code
- 2.13.2.14Analog Signaling Settings: Turnoff Code
- 2.13.2.15Analog Squelch Settings: Invert DCS
- 3Transmitter Assembly and Adjustment
- 3.1Frequency Change
- 3.2Minor Frequency Change
- 3.3Major Frequency Change
- 3.4Digital Signal Processor Board Alignment
- 3.4.1Radio Service Software
- 3.4.2Radio Programming Interface Module Interconnection
- 3.4.3Reference Oscillator Adjustment
- 3.4.4Transmitter Deviation Balance Adjustment
- 3.4.5Transmitter Deviation Limit Adjustment
- 3.4.6Audio Level Alignment
- 3.4.7Amplifier Alignment
- 3.5Recommended Test Equipment List
- 3.6Repair Note
- 3.7Printed Circuit board Numbering Convention
- 4Repeater System Configuration
- 4.1Interim Repeater
- 4.1.1Repeater Interconnect Cable Pinout
- 4.2Project 25 Compliant Repeater
- 4.3Repeater System Troubleshooting
- 5ILLUSTRATIONS
- 5.1Digital Repeater Transmitter Front Panel
- 5.2Digital Repeater Transmitter Exploded View
- 5.3Digital Repeater Transmitter Block Diagram (Interim Mode)
- 5.4Digital Repeater Transmitter Schematic Diagram
- 5.5Digital Repeater Transmitter Main Board Component Layout (Bottom)
- 5.6Digital Repeater Transmitter Main Board Component Layout (Top)
- 5.7Digital Repeater Microprocessor Board Component Layout (Bottom)
- 5.8Digital Repeater Microprocessor Board Component Layout (Top)
- 6PARTS LIST
- 6.1Digital Repeater Transmitter Main Board Parts List
- 6.1.1Digital Repeater Transmitter Main Board Electrical Parts List
- 6.1.2Digital Repeater Transmitter Main Board Mechanical Parts List
- 6.2Digital Repeater Microprocessor Board Parts List
- 6.2.1Digital Repeater Microprocessor Board Electrical Parts List
- 6.2.2Digital Transmitter Additional PCBs
- 7REVISION HISTORY
DE
DANIELS
ELECTRONICS
UT-4R400 UHF Project 25
Digital
Transmitter
Instruction
Manual
2-3
2.7.1
Channel
Select
Line Mapping
The
table
below shows the
relationship
between the states of the
channel
select
lines. Note that the
channel
select
lines follow a binary pattern, but that the binary “0” represents
channel
1.
CSEL3 CSEL2 CSEL1 CSEL0 Channel
selected
LO LO LO LO 1
LO LO LO HI 2
LO LO HI LO 3
LO LO HI HI 4
LO HI LO LO 5
LO HI LO HI 6
LO HI HI LO 7
LO HI HI HI 8
HI LO LO LO 9
HI LO LO HI 10
HI LO HI LO 11
HI LO HI HI 12
HI HI LO LO 13
HI HI LO HI 14
HI HI HI LO 15
HI HI HI HI 16
2.8 Jumper
Functions
and
standard
configuration
Jumper
Default
Position
Function when
installed
JU1 Out Forces HC11 microprocessor to reset mode
JU2 In Enables PTT input from subrack
JU3 In Enables
Unbalanced
audio input from subrack
JU4 In Enables 600 ohm input
impedance
(impedance
about 15k when out)
JU5 Out Allows
Digita
l Signal Processor board to turn on
LVDS
receiver
JU6 Out Forces
LVDS
receiver
on
JU7 Out Connects
LVDS
receiver
output to
Digital
Signal Processor board input
JU8 Out Connects
Digital
Signal Processor board output to
LVDS
transmitter
JU9 Out Allows Di
gital
Signal Processor board to turn on
LVDS
transmitter
JU10 Out Enables
LVDS
bus resistive
termination
JU11 In
Disables
LVDS
transmitter
JU12 In Connects
LH_DATA
signal to J1 for
programming
JU13 In Connects baseband audio from J9 to audio
circuitry
JU14 In Connects
ANALOG_COR*
input from J9
JU15 In Connects
LVDS
bus to J9
JU16 In Connects
LVDS
bus to J9
JU17 In Connects
DIGITAL_COR*
input from J9
JU18 In Connects +8.8VDC to J1 to power RPIM
JU19 In Connects BUSY signal to J1 for
programming
JU20 Out Connects future data port to M-3
motherboard
JU21 Out Connects future data port to M-3
motherboard
JU22 Out Connects future data port to M-3
motherboard
JU23 Out Connects future data port to M-3
motherboard