User`s manual

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5.2.7 50 PIN IO PORT
The 50 PIN IO PORT is a data IO interface connected to an ERNI 054596 0.05-inch header.
There are 44 data lines, 4 dedicated ground lines and 2 lines that can be ground or 3.3 volts,
factory settable only. Each data pair has been designed to support 1 LVDS pair or 2 LVTTL data
lines. There are four (LVTTL or two LVDS) lines that go to FPGA global clock pins. Table 3
shows the 50 PIN IO Connections.
Pin Signal Pin Signal
1 1Negative Data 0 2 1Positive Data 0
3 1Negative Data 1 4 1Positive Data 1
5 1Negative Data 2 6 1Positive Data 2
7 1Negative Data 3 7 1Positive Data 3
9 1Negative Data 4 10 1Positive Data 4
11 1Negative Clock 12 1Positive Clock
13 1Negative Valid 14 1Positive Valid
15 1Negative Sync 16 1Positive Sync
17 Ground 18 Ground
19 1Negative Data 5 20 1Positive Data 5
21 1Negative Data 6 22 1Positive Data 6
23 1Negative Data 7 24 1Positive Data 7
25 Ground/3.3V 26 Ground/3.3V
27 2Negative Data 0 28 2Positive Data 0
29 2Negative Data 1 30 2Positive Data 1
31 2Negative Data 2 32 2Positive Data 2
33 2Negative Data 3 34 2Positive Data 3
35 2Negative Data 4 36 2Positive Data 4
37 2Negative Clock 38 2Positive Clock
39 2Negative Valid 40 2Positive Valid
41 2Negative Sync 42 2Positive Sync
43 Ground 44 Ground
45 2Negative Data 5 46 2Positive Data 5
47 2Negative Data 6 48 2Positive Data 6
49 2Negative Data 7 50 2Positive Data 7
Table 3 50 PIN IO Connector