User manual

SP-5000M-CXP2 / SP-5000C-CXP2
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5.1.3 The relationship between sensor bit, pixel clock and output format.
In the SP-5000-CXP2, there are three sensor bit depths available as well as three pixel clocks, 72
MHz, 57.6 MHz and 48 MHz. The combination of these settings is directly related to which Link
Configuration can be used. The following table shows the available combinations.
Table – 3 Sensor bit, Pixel clock and output format relationship
Note1: By selecting sensor bit depth, available link configuration is determined.
5.1.4 Associated GenICam register
GenICam
Name
Access
Values
Category
Link
Config
R/W
Single3125Gbps
Single625Gbps
Dual3125Gbps
Dual625Gbps
Device Control
Pixel
Format
R/W
[Mono]
Mono8
Mono10
[Color]
BayerGB8
BayerGB10
8 Bit RGB
Image Format Control
Sensor
Pixel
Format
R/W
8bit
10bit
12bit
JAI-Custom
Pixel clock Sensor bit Available Link Configuration Mono Bayer RGB
8bit CXP-6x2/8bit ○ ○ ○
CXP-6x2/8bit ○ ○ -
CXP-6x2/10bit ○ ○ -
CXP-6x2/8bit ○ ○ -
CXP-6x2/10bit ○ ○ -
8bit CXP-6x1/CXP-3x2/8bit ○ ○ ○
CXP-6x1/CXP-3x2/8bit ○ ○ -
CXP-6x1/CXP-3x2/10bit ○ ○ -
CXP-6x1/CXP-3x2/8bit ○ ○ -
CXP-6x1/CXP-3x2/10bit ○ ○ -
8bit CXP-3x1/8bit ○ ○ ○
CXP-3x1/8bit ○ ○ -
CXP-3x1/10bit ○ ○ -
CXP-3x1/8bit ○ ○ -
CXP-3x1/10bit ○ ○ -
72MHz
54MHz
48MHz
10bit
12bit
10bit
12bit
10bit
12bit