Datasheet

M2Y1G64TU88D0B / M2Y2G64TU8HD0B / M2Y1G64TU88D4B / M2Y2G64TU8HD4B / M2Y1G64TU88D4B
M2Y1G64TU88D5B / M2Y2G64TU8HD5B / M2Y1G64TU88D6B / M2Y2G64TU8HD6B
M2Y1G64TU88D7B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2 14
10/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(T
CASE
= 0 °C ~ 85 °C; V
DDQ
= 1.8V ± 0.1V; V
DD
= 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
PC2-5300
PC2-6400
Unit
Min.
Max.
Min.
Max.
Tck
Clock Cycle Time (Average)
3000
8000
2500
8000
ps
Tch
CK high-level width (Average)
0.48
0.52
0.48
0.52
Tck
Tcl
CK low-level width (Average)
0.48
0.52
0.48
0.52
Tck
WL
Write command to DQS associated clock edge
RL-1
RL-1
Nck
Tdqss
Write command to 1
st
DQS latching transition
-0.25
0.25
-0.25
0.25
Tck
Tdss
DQS falling edge to CK setup time (write cycle)
0.2
-
0.2
-
Tck
Tdsh
DQS falling edge hold time from CK (write
cycle)
0.2
-
0.2
-
Tck
Tdqsl,(H)
DQS input low (high) pulse width (write cycle)
0.35
-
0.35
-
Tck
Twpre
Write preamble
0.35
-
0.35
-
Tck
Twpst
Write postamble
0.4
0.6
0.4
0.6
Tck
Tis
Address and control input setup time
200
-
175
-
ps
Tih
Address and control input hold time
275
-
250
-
ps
Tipw
Input pulse width
0.6
-
0.6
-
Tck
Tds
DQ and DM input setup time (differential data
strobe)
100
-
50
-
ps
Tdh
DQ and DM input hold time(differential data
strobe)
175
-
125
-
ps
Tdipw
DQ and DM input pulse width (each input)
0.35
-
0.35
-
Tck
Tac
DQ output access time from CK/
-450
450
-400
400
ps
Tdqsck
DQS output access time from CK/
-400
400
-350
350
ps
Thz
Data-out high-impedance time from CK/
-
t
AC
max
-
tACmax
ps
Tlz(DQS)
DQS low-impedance time from CK/
t
AC
min
t
AC
max
tACmin
tACmax
ps
Tlz(DQ)
DQ low-impedance time from CK/
2t
AC
min
t
AC
max
2t
AC
min
t
AC
max
ps
Tdqsq
DQS-DQ skew (DQS & associated DQ signals)
-
240
-
200
ps
Thp
Minimum half clk period for any given cycle;
defined by clk high (Tch) or clk low (Tcl) time
Min(Tch(abs),
Tcl(abs))
-
Min(Tch(abs),
Tcl(abs))
-
ps
Tqhs
Data hold Skew Factor
-
340
-
300
ps
Tqh
Data output hold time from DQS
t
HP
– t
QHS
-
Thp – Tqhs
-
ps
Trpre
Read preamble
0.9
1.1
0.9
1.1
Tck
Trpst
Read postamble
0.4
0.6
0.4
0.6
Tck
Trrd
Active bank A to Active bank B command
7.5
-
7.5
-
ns
Tfaw
Four Activate Window for 1KB page size
products
37.5
-
35
-
ns
Tccd
 to 
2
2
Nck
Twr
Write recovery time without Auto-Precharge
15
-
15
-
ns
Tdal
Auto precharge write recovery + precharge time
WR+tnRP
-
WR+tnRP
-
Nck
Twtr
Internal write to read command delay
7.5
-
7.5
-
ns
Trtp
Internal read to precharge command delay
7.5
7.5
ns
Tcke
CKE minimum pulse width
3
3
Nck
Txsnr
Exit self refresh to a Non-read command
Trfc+10
-
Trfc+10
ns
Txsrd
Exit self refresh to a Read command
200
-
200
Nck
Txp
Exit precharge power down to any Non- read
command
2
-
2
-
Nck