Datasheet

M2Y1G64TU88D0B / M2Y2G64TU8HD0B / M2Y1G64TU88D4B / M2Y2G64TU8HD4B / M2Y1G64TU88D4B
M2Y1G64TU88D5B / M2Y2G64TU8HD5B / M2Y1G64TU88D6B / M2Y2G64TU8HD6B
M2Y1G64TU88D7B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2 13
10/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
T
CASE
= 0 °C ~ 85 °C; V
DDQ
= V
DD
= 1.8V ± 0.1V (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-5300
PC2-6400
Unit
I DD0
Operating Current: one bank; active/precharge; Trc = Trc (MIN); Tck =
Tck (MIN); DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
1408
1628
Ma
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; Trc
= Trc (MIN); CL=2.5; Tck = Tck (MIN); IOUT = 0Ma; address and control
inputs changing once per clock cycle
1320
1540
Ma
I DD2P
Precharge Power-Down Standby Current: all banks idle;
power-down mode; CKE  VIL (MAX); Tck = Tck (MIN)
176
176
Ma
I DD2N
Idle Standby Current: CS  VIH (MIN); all banks idle; CKE  VIH
(MIN); Tck = Tck (MIN); address and control inputs changing once per
clock cycle
1144
1320
Ma
I DD2Q
Precharge Quiet Standby Current: All banks idle;  is HIGH; CKE
is HIGH; t
CK
= t
CK (MIN)
; Other control and address inputs are stable,
Data bus inputs are floating.
880
968
Ma
I DD3PF
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE
is LOW; Other control and address inputs are STABLE, Data bus
inputs are floating. MRS A12 bit is set to low (Fast Power-down
Exit).
493
528
Ma
I DD3PS
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE
is LOW; Other control and address inputs are STABLE, Data bus
inputs are floating. MRS A12 bit is set to high (Slow Power-down
Exit).
194
194
Ma
I DD3N
Active Standby Current: one bank; active/precharge; CS  VIH
(MIN); CKE  VIH (MIN); Trc = Tras (MAX); Tck = Tck (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
1056
1232
Ma
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and
DQS inputs changing twice per clock cycle; CL=2.5; Tck = Tck (MIN)
1452
1672
Ma
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and
DQS outputs changing twice per clock cycle; CL = 2.5; Tck = Tck
(MIN); IOUT = 0Ma
1584
1804
Ma
I DD5
Auto-Refresh Current: Trc = Trfc (MIN)
1936
2156
Ma
I DD6
Self-Refresh Current: CKE  0.2V
194
194
Ma
I DD7
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data
changing at every transfer; Trc = Trc (min); IOUT = 0Ma.
2156
2420
Ma
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.