Service manual

UCW and Ultraview 1700 Monitors — Service Manual
3-8
Keyboard/Mouse Interface
The keyboard and mouse interface is implemented with the Intel 82C42PE programmable interface
chip on the ISA bus. This device comes pre-programmed with a Phoenix keyboard/PS-2 mouse
BIOS.
EPP Port
A 78C36 device on the ISA bus implements an IEEE 1284, Level 1 electrically-compliant, bi-
directional enhanced parallel port (EPP). The hardware includes a 16-byte deep FIFO and can use
ISA DMA for data transfers. The software is responsible for many functions of the port, including
mode negotiation, RLE compression (decompression can be done in hardware), as well as the
detailed implementation of several of the communication modes. Refer to the IEEE 1284-1994
standard for detailed requirements of the port. This function is not currently supported.
ISA I/O Buffers
These latches and buffers interface miscellaneous low-frequency status and control signals to the
ISA bus.
SDLC Interface
The SDLC interface is the communications interface to Spacelabs Medical modules, which supply
patient data to the system.
Ultraview monitors communicate with the external module devices via the SDLC connector:
• Power is not supplied from this connector. All module power is generated by the DC power supply
and is isolated from the monitor.
• The SDLC interface runs at a 1.892352-MHz frequency. This is divided down to generate a
448-Hz sampling rate. The SDLC communication task has a built-in program that retrieves the
data from the bus, assembles it into a packet format, and provides it to the CPU.
• The SDLC clock signals are sent by the SDLC interface and are used to drive the external SDLC
bus and modules. The SDLC data signals are bi-directional and can be used both to transmit and
receive data from the intelligent modules.
Nurse Alarm Output
When an alarm sounds, a relay that is connected to the nurse alarm connector is activated. When
this connector is connected to an external nurse alarm light/buzzer, the light/buzzer will activate
when an alarm occurs.
Clock Distribution
The clock distribution system is designed to provide low-skew clocks to the core hardware operating
off of the MPC860 and PCI busses. Additional, lower-tolerance clocks are needed in other
peripheral areas.
A Motorola PLL-based clock driver chip is used to provide a low-skew clock distribution system and
several optional operational configurations. This provides clocks to all of the PCI devices under
1.0 ns of skew, including wiring delay variation. The MPC860 and FPGA clock skew falls within this
specification also. The device can be pin-strap programmed for various clock frequencies including
25, 33, and/or 50 MHz.