Service manual

UCW and Ultraview 1700 Monitors — Service Manual
3-6
Main CPU
The UCW/1700 uses a 50-MHz version of the Motorola MPC860 processor.
The following are some of the special 860 features:
• PowerPC core processor unit
• 4 K instruction cache
• 4 K data cache
• Memory management unit with instruction and data TLBs
• Watchdog and event timers
• Interrupt controller
• Programmable chip selects and a DRAM controller for memory and peripheral support
• An internal shared memory and RISC engine, which together perform embedded peripheral
support functions and emulate DMA channels
• Six high-speed dedicated serial peripheral ports
• 64 programmable I/O ports
Memory
Flash, DRAM, and SRAM memory are all on the local 860 bus. NVRAM is on the ISA bus.
Flash Memory — Two banks of flash memory are connected to programmable chip selects
0 and 1. Flash memory is used for code storage and is fast enough so that code can be directly
executed out of flash. This memory may be in-circuit programmed. The flash is mounted on a
socketed DIMM. The DIMM can hold from 2 to 16 Megabytes, with 4 being typical.
DRAM Memory — Four banks of DRAM are connected to chip selects 2, 3, 4, and 5. All DRAM
is 3.3V EDO. The DRAM is mounted on two socketed DIMMs. From 4 to 32 MB of DRAM can
be installed, with 8 being typical. The application program is copied from flash to DRAM upon
boot up and is executed from DRAM.
SRAM (GDS) Memory — 256 KB of DRAM are connected to chip select 6. This SRAM holds
up the global data system (GDS) data. It is typically held up through power interruptions by a
super cap for more than one day.
NVRAM Memory — NVRAM is discussed in the ISA section.
MPC860-PCI Bridge
This is a Spacelabs Medical-designed Field-Programmable Gate Array (FPGA), which implements a
bus bridge between the MPC860 processor and the PCI bus. The 860 accesses all PCI and ISA
devices through this PCI bridge.
The main functions provided by the MPC860-PCI Bridge:
• Allow the 860 processor to access memory, I/O, and configuration address spaces on the PCI
bus.
• Allow PCI peripherals, via their bus mastering capability, to access DRAM and SRAM memory
installed on the 860 processor bus via the 860’s bus mastering capability.
• Support programmable chip selects similarly to the 860 CPU for PCI bus-initiated transactions.
• Convert big endian to little endian and vice versa. The PCI bus is little endian; the 860 bus is big
endian.
• Perform PCI bus central arbiter function.
• Perform 860 processor bus arbitration.