Service manual
Schematic Diagrams
Clock Generator B - 19
B.Schematic Diagrams
Clock Generator
CL K_ PCIE_ M INI_ 3G
Z1740
C 488 *10P_50V_04
C5 3 4
10U_10V_08
Z1726
R279 33_04
BSEL0
SELLCD_27#=0
Z1712
R268 10K_04
C502
0.1U_10V _X7R_04
1
M CH_CLKREQ #
(P E RE Q2 #)
CLK_ BSEL 1 [2,4 ]
REF_14.318M
C LK_ PC IE_N EW_ CAR D#
R284 2.2K_04
DO T 9 6
3.3VM_CLK
C 499 *10P_50V_04
3.3VM_CLK
X3
14.318M Hz
1 2
C LK_ DR EF
C LK _ CP U_ BCL K
C LK_ PC IE_3 G PLL#
C 507 *10P_50V_04
PC I E X9
CL K_ PCIE_ 3 GPL L
R293 *10m il_short
CL K_ ICH 48
Red words must be controlled by BIOS
CLK_ PW RG D[1 5]
Z1733
C LK_ PC IE_M INI#
C 466 *10P_50V_04
R272 33_04
27FIX/SS
C LK_ DR EF#
RN24
4P2RX33_04
1 4
2 3
C468
0.1U_10V_X7R_04
Z1735
Z1704
RN21
4P2RX33_04
14
23
1
SELLCD_27#
PC LK_ IC H33[1 4 ]
MCH _ CL KRE Q # [ 5 ]
667 M Hz16 6 MHz
CL K_ DREF # [5]
L39
HC B1608KF-121T25
WLAN_C LKREQ #
(P E RE Q3 #)
PM _STPPC I#[1 5 ]
CL K_ ICH 14
CLK_ SATA
FSLA
Z1736
R295 300_1% _04
PC I E X9
CL K_ PCIE_ M INI_ 3G #
R271 33_04
U2 2
ICS9 L PR3 63 EG LF
5
11
56
62
49
51
35
48
52
2
6
8
55 16
61
12
42
34
58
57
45
36
33
60
3
4
28
50
54
9
64
13 21
37
53
32
30
31
27
26
24
25
23
22
19
20
18
17
14
15
10
47
7
1
29
46
39
38
41
40
44
43
59
63
PC ICL K3 /*SEL PCIEX0_ LC D#
VD D48
VDD REF
CPU_STOP#
CPUT _ L1F
CPU C_L0
PCIeC_L5
CPU C_ L 1F
CPU T_L0
GND
GN D
PC ICL K_ F4/ITP_ EN
SD ATA FSL B/TEST_M ODE
R EF1/F SLC /TE ST_ SEL
FSL A/U SB_4 8 MH z
VD DPC IEX
* PW RS AVE#
X1
X2
VD DA
PC IeT_L5
*PER EQ4 #
R EF0_14.318M
PC ICL K1
PC ICL K2
VDD PCIEX
VDD CPU
SC LK
* SELLC D_27#/PCIC LK_F5
* *PCIC L K0/R EQ_SEL
GND VD DPC IEX
GND
GND
*PER EQ3 #
PC IeT_L4
PCIeC_L4
SATACLKC_L
SATACLKT_ L
PC IeT_L3
PCIeC_L3
PCIeC_L2
PC IeT_L2
PC IeT_L1
PCIeC_L1
27SS/LCD_SSC GC /PCIeC_L0
27F IX/LCD _SSCG T/PC IeT_L0
PCIe T_ L9/DO TT_ 9 6 MHz L
PCIeC_L9/D OTC_96MHz L
VT T _PW R_ GD /PD#
VR EF
VD DPC I
VDD PCI
GN D
GN DA
PC IeT_L6
PCIeC_L6
PCIeT_L7/PER EQ1#
PC IeC _L7/PER EQ2#
PCIeT_L8/CPU ITP T_L2
PC IeC_ L8 /C PUITPC_ L 2
GN D
PC I/PCIEX_ STOP#
CLK_ PCIE_MIN I [20 ]
C 492 *10P_50V_04
RN28
4P2RX33_04
14
23
RN31
4P2RX33_04
1 4
2 3
C4 71
27 P_ 5 0V_ 0 4
CK505
106 6 MHz
PCIECLK 4 (J M385 )
LCD(96MHz)
C532
0.1U_10V_X7R _04
C 498 *10P_50V_04
C LK_ PC IE_IC H
C LK_ DR EFSS
C 474 *10P_50V_04
BS EL2
CL K_ MC H_B CL K
PCLK_ TPM
Z1723
PCLK_ICH 33
C 509 *10P_50V_04
CL K_ ICH 48
C 449 *10P_50V_04
C LK_ SATA
PCLK_TPM
Z1728
Layout note:
LAN_CLKREQ #
(P E RE Q4 #)
FS LC
IC H_SMBD AT0[10,11,15]
C LK_ PC IE_M INI_3G
XTAL _ IN
PCIECLK 2 (MINI)
3.3VS
CL K_ PCIE_ MIN I_3 G # [19]
CL K_ CPU _B CL K
CL K_ CPU_ BC LK# [2]
CLK_ DR EFSS#
RN26
4P2RX33_04
14
23
C 484 *10P_50V_04
C 494 *10P_50V_04
PCIEX0
PCLK_ ICH 33
C 501 *10P_50V_04
C LK_ BSEL 2[2 ,4 ]
C491
0.1U_10V_X7R_04
PCIECL K 8 ( ICH)
BS EL1
DO T 9 6
3.3VM_CLK
PCLK_ TP M[1 9]
SATACLK
CL K_ DREF SS [5 ]
CLK_ PCIE_GLAN [23]
CL K_ PCIE_ M INI
C LK_ PC IE_M INI_3G#
RN30
4P2RX33_04
1 4
2 3
C 536 *10P_50V_04
C 542 *10P_50V_04
Z1713
C 490 *10P_50V_04
SELPCIEX0_LCD#/
CL K_ PCIE_ G LAN #
R267 33_04
CLK_ICH48[1 5 ]
30mils
CL K_ PCIE_ MIN I_3 G [1 9 ]
Z1725
0
Pin14/15
PCIECL K 3 ( MI NI_ 3G )
C 528 *10P_50V_04
C 497 *10P_50V_04
0
CLK_ SATA#
R296
1K_1% _04
SELLCD_27#=1
LAN _CLKREQ # [23]
CLK_ DR EFSS
C LK_ SATA#
Z1731
CLOCK GENERATOR
Z1730
R269 10K_04
SELLCD_27#=1
R 307 475_1%_04
PCIECL K 1 ( 3GP LL )
CL K_ CPU_ BC LK [2 ]
CL K_ MC H_B CL K #
CLK_ PCIE_GLAN# [23 ]
CLK_ PCIE_ICH [14 ]
Z1741
SELPCIEX0_LCD#/
CLK_ PCIE_J M380 # [22 ]
C 481 *10P_50V_04
Insatlled: Differential clock
level is higher
PCI ECLK 6 (NEW CARD)
CLK_ PCIE_N EW_C ARD
PCLK_ KBC
C 541 *10P_50V_04
C 512 *10P_50V_04
C LK_ DR EFSS#
Z1732
Z1729
C 537 *10P_50V_04
R253 *10K_04
C 475 *10P_50V_04
CLK_ PCIE_N EW_C ARD #
Fr eq uen cy
PCIEX0
CL K_ PCIE_ M INI#
Layout note:
CLK_ PCIE_3 GPLL [5]
CL K_ PCIE_ J M38 0
Z1742
3.3VS
PCLK_ KBC
C LK_ MC H_BC LK
RN32
4P2RX33_04
1 4
2 3
0
Z1724
PCLK_ KBC[2 6]
C 450 *10P_50V_04
Z1710
C LK_ PC IE_M INI
PCI3 = 1 (high)
Z1711
C LK_ PC IE_3 G PLL
PLACE CRYSTAL WITHIN
50 0 MI L S OF
ICS9LPR363EGLF
20 0 MHz
CL K_ CPU _B CL K #
C511
1U_6.3V_04
SATA_CLKREQ#
(P E RE Q1 #)
800 M Hz
Z1718
C LK_ PC IE_G LAN
C 533 *10P_50V_04
FSLA
PM_ STPCPU #[15 ]
CLK_ PCIE_ICH # [14]
CL K_ DREF SS # [5 ]
C LK_ MC H_BC LK#
SELPCIEX0 _ LC D#
PCI3 = 0 (low)
CL K_ PCIE_ IC H
Z1719
CLK_ PCIE_J M380 [22 ]
CLK_PCIE_3GPLL#
CL K_ PCIE_ G LAN
Z1715
Z1738
Z1703
C LK _ CP U_ BCL K#
H os t Clo ck
Z1722
PCIECL K 5 ( GLAN)
3.3VS
CLK_MCH _BCLK# [4]
C4 72
27P_50V_04
0
WLA N_CLKREQ # [19,20]
Z1714
C478
* 10U _10V_08
RN22
4P2RX33_04
1 4
2 3
De f a ul t
Place termination close
to ICS9LPR363DGLF
CL K_ DR EF#
C 519 *10P_50V_04
Z1727
C4 6 7
1U _6.3V_04
C 487 *10P_50V_04
1
CL K_ MCH _BCL K [4 ]
C LK_ PC IE_IC H#
CL K_P CIE _ NE W _ CA RD# [20 ]
C4 82
0.1U _10V_X7R_04
0
CL K_ ICH 14
FSLC
C 543 *10P_50V_04
R282 *100K_04
Pin5
REQ _ SEL
C 505 *10P_50V_04
Layout note:
3.3V S[5 ,8 ..16 ,19. .27 ,3 1]
CL K_ PCIE_ J M38 0#
C LK_ PC IE_N EW_ CAR D
CLK_ICH14[1 5 ]
26 6 MHz
SATA _C LKR EQ# [15 ]
IC H_SMBC LK0[10,11,15]
XTAL _ OU T
C480
0.1U_10V_X7R _04
RN29
4P2RX33_04
14
23
20mils
Pin17/18
C LK_ BSEL 0[2 ,4 ]
CL K_ DREF [5 ]
C 544 *10P_50V_04
FS LB
CLK_ SATA# [13 ]
C LK_ PC IE_J M 38 0
Pi n 9
CLK_ SATA [13]
CLK_P CIE_NEW_CA RD [20]
RN23
4P2RX33_04
14
23
C535
10U_10V _08
C500
1U _6.3V_04
R 306 475_1%_04
CL K_ PCIE_ IC H#
C LK_ PC IE_J M 38 0#
ITP_E N
0
CLK_ PCIE_3 GPLL # [5]
40mils
CL K_ PCIE_ MIN I# [2 0]
FSLB
R265 10K_04
R266 *33_04
RN25
4P2RX33_04
14
23
SELLCD_27#=0
CL K_ DR EF
C LK_ PC IE_G LAN#
RN27
4P2RX33_04
14
23
Sheet 18 of 40
Clock Generator