Service manual
Schematic Diagrams
Intel Penryn (Socket-P) 1/2 B - 3
B.Schematic Diagrams
Intel Penryn (Socket-P) 1/2
Sheet 2 of 40
Intel Penryn
(Socket-P) 1/2
H_ B NR # [4 ]
R5 1K_1%_04
H_A#4
H_D#63
V_TH RM
TR 1
*TSM1A103H34D 3R
CL K _ CP U_ BC LK # [18 ]
H _ DS T BN# 0[4 ]
H_NMI[13]
C PU_BSEL 1[4,1 8]
H_ D# 27
H_ DE F ER # [4]
H _A#26
R4
2K_1% _04
H_DSTBN#2 [4]
THER M_RST#[2 6 ]
H_ D# 25
H_A#9
H _A#18
H _A#[35:3][4 ]
H_DBSY # [4]
H_ HIT M# [4]
H_A#7
H _A#34
H_PREQ#
H_ D# 28
C3 3 7
*0.01U _16V_X7R _04
1.05VS
C336
1U _6.3V_04
H_ TH ERM DA
H_ D# 21
H_ D# 6
H_ D# 1
H_D#41
H_D#44
H_ RS # 2 [4 ]
H_D#59
H_ D# 19
H _A#10
COMP2
H_ D# 23
R8
54.9_1%_04
R2 0 0
*1 0 0K _ 0 4
H_ D# 26
PM _THR M# [1 5 ]
COMP2
H_D#33
SM C_CPU _THE RM [26 ]
H_ D# 31
H_ D# 29
C7
*1U_6.3V_X5R_06
? ADT7421 Colay
PS I# [31 ]
H_D#57
R2 1 1
*330K_04
H_ RS # 1 [4 ]
H _A#25
H_REQ#2
R7 54.9_1%_04
H_ DIN V # 1[4]
R 197 56_04
H_ A DS# [4]
H_DINV#3 [4]
H _A#12
H_ D# 30
H_REQ#4
H_D#53
H _A#14
R 173 54.9_1% _04
R2 09
*100K_04
ADDR
GROUP_0
ADDR
GROUP_1
CONTROL
XD P /I TP S I GNALS
H C LK
TH ERM A L
RE SE RV ED
ICH
U9 A
MOLEX_47430-6215
N3
P5
P2
L2
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
J4
U2
V4
M4
N5
T2
V3
B2
D2
D22
L5
L4
K5
M3
N2
J1
A6
H1
M1
V1
D3
A22
A21
E2
AD 4
AD 3
AD 1
AC 4
G5
F1
C2 0
E1
H5
F21
A5
G6
E4
D2 0
C4
B3
C6
B4
H4
AC 2
AC 1
D2 1
K3
H2
K2
J3
L1
C1
F3
F4
G3
A3
D5
AC 5
AA6
AB3
C7
A24
B25
AB5
G2
AB6
W3
AA4
AB2
AA3
F6
A[10 ]#
A[11 ]#
A[12 ]#
A[13 ]#
A[14 ]#
A[15 ]#
A[16 ]#
A[17 ]#
A[18 ]#
A[19 ]#
A[20 ]#
A[21 ]#
A[22 ]#
A[23 ]#
A[24 ]#
A[25 ]#
A[26 ]#
A[27 ]#
A[28 ]#
A[29 ]#
A[3]#
A[30 ]#
A[31 ]#
R SVD[01]
R SVD[02]
R SVD[03]
R SVD[04]
R SVD[05]
R SVD[06]
R SVD[07]
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A2 0 M#
ADS#
AD STB [0]#
AD STB [1]#
R SVD[08]
BCLK[0 ]
BCLK[1 ]
BN R#
BPM[0 ]#
BPM[1 ]#
BPM[2 ]#
BPM[3 ]#
BPRI#
BR 0#
DBR#
D BSY#
DEFER#
DRD Y#
FER R#
HI T#
HIT M#
IER R#
IG NNE #
INI T#
LINT0
LINT1
LO C K #
PRD Y#
PR EQ#
PROCHOT#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
RES E T#
RS[0 ]#
RS[1 ]#
RS[2 ]#
SM I#
STPCL K#
TC K
TDI
TD O
THER MTRIP#
TH E R M D A
THER MD C
TM S
TRD Y#
TRS T#
A[32 ]#
A[33 ]#
A[34 ]#
A[35 ]#
R SVD[09]
H _A#31
H_ RS # 0 [4 ]
H_D#34
R195 *10mil_short
V_T H RM
SM D_CPU _THE RM [26 ]
PM_ T HRM TRIP# [5 ,1 3,2 8 ]
COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
COMP1, COMP3: 0.5" Max, Zo=55 Ohms
Best estimate is 18 mils wide trace for outer
layers and 14 mils wide trace if on internal
layers.
Put it at central of
CPU socket
H_ HIT # [4 ]
H _DPRSTP# [5,13,31]
CPU ONLY SUPPORT TO 35W
CL K _ CP U_ BC LK [18]
H_DSTBN#1[4 ]
H_D#50
H_A#5
H_D#47
H_D#42
R1 9 3 * 0_ 0 4
3.3V
3. 3 V[1 2..1 7 ,1 9,2 0 ,23 ,2 9 ,30 ]
H_REQ#3
COMP3
H_ INIT # [1 3 ]
H_ D# [63:0 ][4 ]
H_D#38
H _A#13
H_ D# 22
R 171 649_1%_06
Q18 *AO3409
G
DS
Layout Note:
H _PR EQ#
H_ D# 10
U1 3
aS C 75 2 5
1
2
3
4
5
6
7
8
VD D
D+
D-
THER M
GND
ALER T
SDA TA
SC LK
H _A#16
H _A#28
H_ D# 4
H_ D# 11
H_D#55
H_ T RDY # [4 ]
H_ DST BP# 1[4]
H_D#52
H_PROCHOT#
H_D#51
R6
27.4_1%_04
1.05VS[3..5,7,8,13,16,29]
CPU_ BSEL 0
C335
1000P_50V_X7R_04
H_ D# 17
H_ T HE RM DC
H_ B PRI# [4]
H_TDI
H_D#61
10mils
H_TMS
CPU_ BSEL 1
H_CPURST#
Route H_THERMDA and
H_THERMDC on same layer.
10 mil trace on 10 mil spacing.
1. 0 5 V S
H_A#6
H _A#17
H _A#32
H_TCK
COMP0
H _A#29
H_IERR#
THER M_ALERT# [26]
H_AD STB# 1[4 ]
R210 *10m il_short
H_D#45
R1 8 2
54.9_1%_04
12mils
H_INTR[13]
Layout Note:
H_ D# 3
H _A#11
H_ D# 12
COMP1
H_ CP U RST# [4 ]
COMP0
H_D#46
H_ D# 16
H_TDI
H_ D# 20
H_ P R OCH OT#
H_D#48
H_ D# 24
0.5" max, Zo= 55 Ohms
H _A#23
H_D#54
Near to Thermal
IC
H_D#62
H _ DPSL P# [13]
R1 8 3
27.4_1%_04
COMP3
H_D#58
H_D#32
H_ T HE R MDC _ R
H_DINV#2 [4]
H_DSTBP#3 [4]
R196 *10mil_short
H_ S T PCL K#[13]
COMP1
CPU_ BSEL 2
H_REQ#1
H _A#21
H _A#30
H_TRST#
R1 9 4
10K_04
H_D#60
H_D#56
D15
ASD75 1V
AC
CPU TEM P [2 6 ]
H_ D# 8
H_IGNNE#[13 ]
H _A#15
H_ D# 18
H_DSTBP#2 [4]
H_A#8
H_TRST#
H_ D# 2
H_ REQ #[4 :0][4]
H_IERR#
H_ D# 5
H_D#39
R 19 *51_1% _04
H_ DR DY # [4]
H _A#24
H_D#49
H _A#[35:3][4 ]
H_REQ#0
H_ D# 15
R 198 54.9_1% _04
Q1 9
*2N7002W
G
DS
Layout note:
H_ TH ERM DC
H _A#19
H_ D# 7
H _A#22
Layout Note:
H _A20M#[1 3 ]
DATA GRP 0 DATA GRP 1
DATA GRP 2DATA GRP 3
MIS C
U9 B
MOLEX_47430-6215
R2 6
U2 6
AA1
Y1
E2 2
F24
J24
J23
H22
F26
K2 2
H23
N22
K2 5
P2 6
R23
E2 6
L23
M24
L22
M23
P2 5
P2 3
P2 2
T24
R24
L25
G22
T25
N25
Y22
AB24
V24
V26
V23
T22
U2 5
U2 3
F23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
AE24
AD24
G25
AA21
AB22
AB21
AC26
AD20
AE22
AF2 3
AC25
AE21
AD21
E2 5
AC22
AD23
AF2 2
AC23
E2 3
K2 4
G24
AF 1
H25
N24
U2 2
AC20
E5
B5
D2 4
J26
L26
Y26
AE25
H26
M26
AA26
AF2 4
AD 2 6
AE6
D6
D7
C24
B2 2
B2 3
C21
D25
AF2 6
A2 6
C23
C3
CO MP [0 ]
CO MP [1 ]
CO MP [2 ]
CO MP [3 ]
D[0]#
D[1]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
D[16]#
D[17]#
D[18]#
D[19]#
D[2]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[3]#
D[30]#
D[31]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[4]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[5]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[6]#
D[60]#
D[61]#
D[62]#
D[63]#
D[7]#
D[8]#
D[9]#
TEST5
D INV[0 ]#
D INV[1 ]#
DINV[2 ]#
DINV[3 ]#
DPRST P#
DPS L P #
DPWR#
DSTBN[0]#
DSTBN[1]#
DST B N[2 ]#
DST B N[3 ]#
D STBP[0]#
D STBP[1]#
DSTBP[2]#
DSTBP[3]#
GTLREF
PSI#
PW RG OO D
SLP#
TEST3
BSE L[0 ]
BSE L[1 ]
BSE L[2 ]
TEST2
TEST4
TEST6
TEST1
TEST7
H_ D# [63:0 ][4 ]
H_ T HE RM DA
R192 *10mil_short
H_D#[63:0] [4]
H_PWRGD [13]
H_AD STB# 0[4 ]
H_ L OCK# [4]
Layout Note:
H _A#33
H _A#27
H_TMS
C PU_BSEL 2[4,1 8]
H _A#35
H_D#36
H_ B REQ # [4 ]
H_DSTBN#3 [4]
H_A#3
R 181 54.9_1% _04
H_CPUSLP# [4]
H_D#40
CPU_GTLREF
H_ F E RR #[1 3]
H_DINV#0[4 ]
H_ D# 9
H_D#43
R 174 54.9_1% _04
H_DSTBP#0[4]
H_ D# 14
H_SMI#[13]
H_D#[63:0] [4]
H_ D# 0
C PU_BSEL 0[4,1 8]
H_DPWR# [4]
H_D#35
H_D#37
H_ D# 13
CPU_GRFE=0.7V
H _A#20
H_TCK
H_THER MDA_R
H_CPURST#
C8
0.01U_16V_X7R _04