Service manual

Schematic Diagrams
B - 4 ATHLON 64 2/4
B.Schematic Diagrams
ATHLON 64 2/4
+1.3V
+2.6V
+2.6V
+2.6V
+2.6V
+2.6V
+1.3V
+1.3V
DQM[0..7][6,7]
MEMDQS[0..7][6,7]
MEMDATA[0..63][6,7]
MEMRASA_L [6,7]
MEMCASA_L [6,7]
MEMWEA_L [6,7]
MEMCASB_L [6,7]
MEMRASB_L [6,7]
MEMBANKB1 [6,7]
MEMBANKA0 [6,7]
MEMCS_L0 [6,7]
MAB[0..13] [6,7]
MEMBANKA1 [6,7]
MEMBANKB0 [6,7]
MEMCLK_L7[6]
MEMCLK_L6[6]
MEMCLK_L5[6]
MEMCLK_L4[6]
MEMCLK_H5[6]
MEMCLK_H4[6]
MEMCKEB [6,7]
MEMCKEA [6,7]
MEMCLK_H6[6]
MAA[0..13] [6,7]
MEMWEB_L [6,7]
MEMCLK_H7[6]
+1.3V [4,7,32]
+2.6V [2,4,5,6,7,14,31,32]
MEMCS_L1 [6,7]
MEMCS_L2 [6,7]
MEMCS_L3 [6,7]
MAB13
MAA4
MMDATA52 MMDATA35 MMDATA34 MMDATA32
MAB9
RSVD_MAA15
MEMCKEB
MMDATA54
MMDATA8
RSVD_MAB14
MAB8
MMDATA18
MEMCS_L5 MMDQS4
MMDATA47 MMDATA31
MMDATA0
MAB5
MAB0
MMDATA20 MMDATA25 MMDATA29
MEMDQS9 MMDQS7
MMDATA38
MMDATA6 MMDATA2
MEMZP
MAB6
MEMBANKB1
MAA8
MEMDQS10
MMDATA60 MMDATA58 MMDATA13 MMDATA11
MMDATA9
MEMBANKB0 MEMCASA_L
MEMDQS12
MMDATA51 MMDATA43 MMDATA42
MEMZN
MAB10
MMDATA30
MEMBANKA1
MMDATA49
MAB11
MAA11
MEMCS_L2 MEMCS_L1 MEMDQS15 MMDQS0
MMDATA4
MEMRESET_L MEMRASB_L
MMDATA19 MMDATA23 MMDATA24 MMDATA26
MAA9
MEMCS_L4 MMDQS1
MMDATA62 MMDATA50 MMDATA48 MMDATA33
MAA6
MAA0
MEMDQS13
MMDATA39 MMDATA37 MMDATA36
MEMCS_L6
MEMCLK_L6
MEMDQS11 MMDQS5
MMDATA56
MAB4
MAB1
MMDATA16 MMDATA27 MMDATA28
MEMWEA_L
MMDQS3 MMDQS2
MMDATA63 MMDATA40 MMDATA10
MEMWEB_L
RSVD_MAB15
MMDATA17 MMDATA22
MEMBANKA0
MEMCS_L3
MMDATA59 MMDATA57 MMDATA55 MMDATA44
MMDATA3
MEMCASB_L
MAB2
MMDATA15
RSVD_MAA14
MAA10
MAA5
MAA3
MEMCLK_L7
MMDATA12
MAB3
MAA12
MMDATA46
MMDATA1
MAB12
MMDATA21
MAA13
MAA1
MEMRASA_L
MEMCS_L7
MEMCKEA
MEMDQS16 MEMDQS14
MMDATA61 MMDATA53 MMDATA45 MMDATA41
MMDATA7 MMDATA5
MAB7
MAA7
MAA2
MEMCLK_L5
MMDQS6
MMDATA14
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
MEMDQS17
MMDQS8
MEMCLK_H5
MEMCLK_H4
MEMCLK_H6
MEMCLK_H7
MEMCLK_L4
MEMCLK_H1
MEMCLK_H0
MEMCLK_L0
MEMCLK_L1
MMDATA16
MMDATA39
MEMDATA28
MMDATA14
MMDATA48
MMDQS6
MEMDATA44
MMDATA29
MEMDATA4
MEMDQS11
MMDATA18
MEMDQS7
MEMDATA53
MEMDATA12
MEMDATA27
MMDATA40
MMDATA7
MEMDATA36
MMDQS2
DQM1
MMDATA49
MEMDATA59
MEMDATA42
MEMDATA61
DQM5
MMDATA38
MEMDATA19
MMDQS3
MMDATA59
MMDATA31
MMDATA51
MEMDATA31
MEMDATA18
MMDATA45
MMDATA5
MEMDQS12
MMDATA6
MEMDATA40
MMDATA42
MMDATA26
MEMDATA2
MMDATA3
MEMDATA43
MEMDATA63
DQM6
MEMDATA34
MEMDQS16
MEMDATA24
MMDQS5
MMDATA24
MMDATA36
MMDATA37
MMDATA60
MEMDATA33
MEMDATA54
MMDATA46
MEMDATA29
MEMDATA8
MEMDQS6
DQM3
MMDATA15
MEMDATA39
MEMDATA14
MEMDATA6
MEMDATA7
MMDATA52
MMDATA32
MEMDATA49
MMDATA63
MMDATA28
MMDATA12
MEMDQS3
MEMDATA45
MEMDQS9
MEMDATA57
MEMDATA41
MEMDATA32
MMDATA47
MMDATA54
MMDATA34
MMDATA4
MEMDQS14
MMDATA2
MEMDATA51
MMDATA8
MEMDATA38
MEMDATA55
MMDATA23
MEMDATA3
MMDATA50
MMDATA56
MEMDATA37
MEMDATA22
MEMDATA47
DQM7
MEMDATA16
MMDATA61
MEMDATA60
MEMDATA5
MMDATA30
MEMDQS1
MEMDATA46
MEMDQS5
MMDATA43
MEMDATA50
MEMDATA58
MEMDQS13
MMDATA22
MMDATA33
MMDATA41
MMDATA57
MMDATA58
MEMDATA15
DQM2
MEMDATA30
MEMDQS10
DQM0
MEMDATA48
DQM4
MMDATA27
MMDATA19
MMDATA44
MEMDQS15
MMDATA13
MEMDATA23
MMDATA53
MEMDATA25
MEMDATA26
MMDQS7
MEMDATA17
MEMDATA52
MMDATA62
MMDATA55
MMDATA25
MEMDATA62
MEMDATA56
MMDATA17
MMDQS1
DDRVREF_CPU
MEMDQS2
MEMDATA13
MMDATA21MEMDATA21
MEMDATA20 MMDATA20
MMDATA35
MEMDQS4
MEMDATA35
MMDQS4
MEMCS_L0
MEMCLK_L4
MEMCLK_L5
MEMCLK_L7
MEMCLK_L6
MEMCLK_H7
MEMCLK_H6
MEMCLK_H4
MEMCLK_H5
MEMDATA1
MEMDATA0 MMDATA0
MMDATA1
MEMDQS0 MMDQS0
MMDATA11
MEMDATA10 MMDATA10
MEMDATA9
MEMDATA11
MMDATA9
R117 10K_04
C559
0.1u_X7R_04
RN6 8P4RX10_04021
2
3
4 5
6
7
8
RN7 8P4RX10_04021
2
3
4 5
6
7
8
C584
0.1u_X7R_04
C609
0.1u_X7R_04
C193
0.22u_04
C558
0.1u_X7R_04
C155
0.22u_04
RN5 8P4RX10_04021
2
3
4 5
6
7
8
C569
0.1u_X7R_04
C676
0.22u_04
T18
C175
0.22u_04
C581
0.22u_04
T12
R349 120_1%
C188
0.22u_04
C587
0.22u_04
R370 10
RN51 8P4RX10_04021
2
3
4 5
6
7
8
C184
0.22u_04
ATHLON 64 (B)
U25B
ZIF_SOCKET754
AG12 D14 C14 A18 B17 C17 D17 AF16 AG16 AH16 AJ17 AG10
AJ16 AJ14 AJ12 AG11 AJ15 AH15 AJ11 AH11 AJ10 AJ9 AH5 AG5 AH9 AJ7 AJ6 W1 M1 L2 J2 G3 L1 L3 G1 G2 F1 E3 B3 A3 E1 E2 A4 C5 B5 A5 A9 C11 A6 C7 B9 A10 A11 C13 A15 A17 B11 A12 B15 A16
AJ13 AJ8 AJ2 AB1 J1 D1 A8 A14 T1 AH13 AH7 AG1 AA1 H1 C2 A7 A13 R1 AE8 AE7
P4
P5
K4
V4
AE10
AG8
E11
C10
P3
R5
K5
V3
AF10
AF8
E12
D10
E5 C4 E6 D6 E7 E8 C8 D8 H5 D4 G5 H3 K3
N5
T3
T5
V5
Y3
AB4
Y5
AD3
AB5
AE5
M5
AF3
AE6
E10
C12
E13
W3 AC1 AC3 W2 Y1 AC2 AD1 AE1 AE3 AG3 AJ4 AE2 AF1 AH3 AJ3 AJ5
J5 L5
M3
T4
U5
W5
Y4
AB3
AA5
AD4
AC5
AD5
M4
AF4
AF6
E9
D12
E14
U2
U1
P1
N2
V1
U3
N1
N3
H4 F5 F4
MEMVREF1 MEMZN MEMZP VTT_A1 VTT_A2 VTT_A3 VTT_A4 VTT_B1 VTT_B2 VTT_B3 VTT_B4 MEMRESET_L
MEMDATA0 MEMDATA1 MEMDATA2 MEMDATA3 MEMDATA4 MEMDATA5 MEMDATA6 MEMDATA7 MEMDATA8 MEMDATA9
MEMDATA10 MEMDATA11 MEMDATA12 MEMDATA13 MEMDATA14 MEMDATA31 MEMDATA32 MEMDATA33 MEMDATA34 MEMDATA35 MEMDATA36 MEMDATA37 MEMDATA38 MEMDATA39 MEMDATA40 MEMDATA41 MEMDATA42 MEMDATA43 MEMDATA44 MEMDATA45 MEMDATA46 MEMDATA47 MEMDATA48 MEMDATA49 MEMDATA50 MEMDATA51 MEMDATA52 MEMDATA53 MEMDATA54 MEMDATA55 MEMDATA56 MEMDATA57 MEMDATA58 MEMDATA59 MEMDATA60 MEMDATA61 MEMDATA62 MEMDATA63
MEMDQS0 MEMDQS1 MEMDQS2 MEMDQS3 MEMDQS4 MEMDQS5 MEMDQS6 MEMDQS7 MEMDQS8 MEMDQS9 MEMDQS10 MEMDQS11 MEMDQS12 MEMDQS13 MEMDQS14 MEMDQS15 MEMDQS16 MEMDQS17 MEMCKEA MEMCKEB
MEMCLK_L0
MEMCLK_L1
MEMCLK_L2
MEMCLK_L3
MEMCLK_L4
MEMCLK_L5
MEMCLK_L6
MEMCLK_L7
MEMCLK_H0
MEMCLK_H1
MEMCLK_H2
MEMCLK_H3
MEMCLK_H4
MEMCLK_H5
MEMCLK_H6
MEMCLK_H7
MEMCS_L0 MEMCS_L1 MEMCS_L2 MEMCS_L3 MEMCS_L4 MEMCS_L5 MEMCS_L6 MEMCS_L7 MEMRASA_L MEMCASA_L MEMWEA_L MEMBANKA0 MEMBANKA1
MEMADDA0
MEMADDA1
MEMADDA2
MEMADDA3
MEMADDA4
MEMADDA5
MEMADDA6
MEMADDA7
MEMADDA8
MEMADDA9
MEMADDA10
MEMADDA11
MEMADDA12
MEMADDA13
NC_C12
NC_E13
MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15
MEMBANKB0 MEMBANKB1
MEMADDB0
MEMADDB1
MEMADDB2
MEMADDB3
MEMADDB4
MEMADDB5
MEMADDB6
MEMADDB7
MEMADDB8
MEMADDB9
MEMADDB10
MEMADDB11
MEMADDB12
MEMADDB13
NC_D12
NC_E14
MEMCHECK0
MEMCHECK1
MEMCHECK2
MEMCHECK3
MEMCHECK4
MEMCHECK5
MEMCHECK6
MEMCHECK7
MEMRASB_L MEMCASB_L MEMWEB_L
C603
0.1u_X7R_04
RN48 8P4RX10_04021
2
3
4 5
6
7
8
+
C571
220u_6.3V_7343
12
+
C200
*220u_4V_7343
12
R113 10K_04
RN47 8P4RX10_04021
2
3
4 5
6
7
8
C604
0.22u_04
RN46 8P4RX10_04021
2
3
4 5
6
7
8
T19
C610
0.22u_04
T14
R185 10_04
RN43 8P4RX10_04021
2
3
4 5
6
7
8
C588
4.7u_08
R372 10
R352 120_1%
C582
4.7u_08
C167
0.22u_04
R178 10
C562
0.22u_04
R104
2K_1%
R351 120_1%
C189
4.7u_08
RN4 8P4RX10_04021
2
3
4 5
6
7
8
RN42 8P4RX10_04021
2
3
4 5
6
7
8
T11
R106 10K_04
RN50 8P4RX10_04021
2
3
4 5
6
7
8
R90 34.8_1%
R371 10
R186 10
R103
2K_1%
R187 10
C166
0.22u_04
C190
4.7u_08
R83 34.8_1%
RN10 8P4RX10_04021
2
3
4 5
6
7
8
T13
RN40 8P4RX10_04021
2
3
4 5
6
7
8
RN3 8P4RX10_04021
2
3
4 5
6
7
8
R369 10
RN11 8P4RX10_04021
2
3
4 5
6
7
8
C178
1000p_04
RN49 8P4RX10_04021
2
3
4 5
6
7
8
C570
0.1u_X7R_04
RN9 8P4RX10_04021
2
3
4 5
6
7
8
R177 10
R350 120_1%
C590
0.1u_X7R_04
RN41 8P4RX10_04021
2
3
4 5
6
7
8
T21 T20
RN8 8P4RX10_04021
2
3
4 5
6
7
8
R184 10_04
T15
C177
0.1u_X7R_04
R114 10K_04
DDRVREF : 5 mil
Trace 10 mil Space
Place within 1 inch
+1.3V VDDIO/2
Memory I/O Compensation
MemReset_L is used to reset the register as required to support the Suspend to Ram state (ACPI S3).
125mA
MEMCLK_H[4..7]
route 5/5/20.
MEMCLK_L[4..7]
route 5/5/20.
MEMDQS[0..17]
route 5/5/20.
PLACE WITHIN 0.25 - 1.00 INCH FROM CPU
place close to socket
PLACE ON BACK SIDE OF CPU
Sheet 3 of 44
ATHLON 64 2/4