Service manual

Schematic Diagrams
Clock Generator (71-M1900-D02) B - 6
Schematic Diagrams
Clock Generator
Sheet 4 of 34
Clock Generator
VCCP
+2.5VS
+3VS
+3VS+3VS
+3VS
+3VS
+2.5VS
+3VS
+3VS
+3VS
AGPCLK (5)
HCLK-650 (5)
ZCLK0 (9)
REFCLK1 (14)
PCICLKPCM (17)
HCLK-CPU# (3)
SDCLK (6)
HCLK-CPU (3)
CLKAPIC (14)
REFCLK0 (9)
PCICLK1394 (19)
HCLK-650# (5)
ZCLK1 (12)
PCICLKIO (20)
FWDSDCLKO(6)
PCICLK961 (12)
PCICLKH8 (22)
PCICLKLAN (21)
BSEL0 (3)
BSEL1 (3)
SMBCLK (7,14,22)
SMBDAT (7,14,22)
CPUSTP#(14,23)
SIO48M (20)
UCLK48M (15)
PCLK_80P (18)
DDRCLK3(7)
DDRCLK5(7)
DDRCLK#3(7)
DDRCLK#5(7)
DDRCLK0(7)
DDRCLK#0(7)
DDRCLK#2(7)
DDRCLK2(7)
DDRCLK4(7)
DDRCLK#4(7)
DDRCLK1(7)
DDRCLK#1(7)
HCLK-CPU
HCLK-CPU#
HCLK-650
HCLK-650#
SDCLK
AGPCLK
ZCLK0
UCLK48M
FB_IN
FS3
FS2
FS0
FS1
MULTISEL
FS4
DDRCLK3
DDRCLK5
DDRCLK#3
DDRCLK#5
FB_IN
BUF_2.5VS
FB_OUT
FB_IN
BUFFERVCC
FWDSDCLKO
SMBCLK
SMBDAT
REFCLK0
REFCLK1
CLKAPIC
HCLK-CPU
HCLK-CPU#
HCLK-650
HCLK-650#
AGPCLK
GCLK_AGP
ZCLK0
ZCLK1
PCICLK961
PCICLK1394
PCICLKH8
SDCLK
PCICLKIO
PCICLKLAN
PCICLK961
PCICLK1394
PCICLKPCM
PCICLKH8
PCICLKIO
PCICLKLAN
ZCLK1
FS0
FS1
SMBDAT
FS2
FS3
MULTISEL
FS4
SMBCLK
CLK_VCC3
PCICLKPCM
UCLK48M
SIO48M
PCLK_80P
DDRCLK0
DDRCLK#0
DDRCLK#2
DDRCLK2
DDRCLK4
DDRCLK#4
DDRCLK1
DDRCLK#1
L65
BK2125HS121
1 2
L67
BK1608HS121
1 2
U19
CLOCK BUFFER (DDR48)
22
8
9
20
18
6
11
15
28
19
21
1
5
14
16
25
27
2
4
13
17
24
26
3
12
7
23
10
SDATA
CLK_IN
NC
FB_IN
NC
GND
GND
GND
GND
FB_OUT
NC
CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
VDD
VDD
SCLK
VDD
AVDD
C600 10PF(R)
C505
0.1UF
C594
10PF
C593
10PF
C574
0.1UF
L68
BK2125HS121
1 2
L21
BK1608HS121
1 2
C474 10PF(R)
C560
10UF/16V
C598
10PF(R)
C557
10PF(R)
C491
10UF/16V
C481
10UF/16V
C573
0.01UF
C569
0.1UF
C504
0.01UF
C552
0.1UF
C131
10UF/16V
C110
0.01UF
C475
0.1UF
C558
10PF(R)
C503
0.1UF
C109
0.1UF
C584
10UF/16V
C583
0.1UF
C562
0.1UF
C556 10PF(R)
C577
10PF(R)
C578 10PF(R)
C597 10PF(R)
C130
0.1UF
R457
10K
R422
10K
C563
0.1UF
C586
0.1UF
C589
0.1UF
C572
0.1UF
C565
0.1UF
C590
0.1UF
R352
22
R503 33
R426 22
R427
22
R505 22
R428 22
R506 22
R517 4.7K(R)
R477 33
R476 33
R398
49.9_1%
R397
49.9_1%
R432
0(R)
R396
49.9_1%
R504
33
R395
49.9_1%
RP76
4P2R-33
1
2 3
4
R516 4.7K(R)
R507 4.7K(R)
R510 4.7K
R512 4.7K
Q17
2N3904
B
E
C
R487
4.7K
R486
4.7K
R509 33
Q18
2N3904
B
E
C
R511
33
C596 10PF(R)
C599 10PF(R)
R456
10K
RP62
4P2R-0
1
2 3
4
RP77
4P2R-33
1
2 3
4
R423
10K
U25
CLOCK GEN (650)
1
3
2
6 7
14
16
17
20
21
22
30
31
27
26
34
35
44
40
36
37
47
39
43
23
4
9
10
15
38
5
8
18
24
25
32
41
11
13
19
28
29
42
48
46
12
45
33
VDDREF
REF1/FS1
REF0/FS0
XIN XOUT
PCICLK_F0/FS3
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
AGPCLK1
AGPCLK0
48M
24_48M/MULTISEL
SDATA
SCLK
CPUCLK1
CPUCLK0
VDDA
VSSA
SDCLK
CPUCLK#0
CPUCLK#1
PCICLK5
REF2/FS2
ZCLK0
ZCLK1
PCICLK_F1/FS4
IREF
VSSREF
VSSZ
VSSPCI
VSSPCI
VSS48
VSSAGP
VSSCPU
VDDZ
VDDPCI
VDDPCI
VDD48
VDDAGP
VDDCPU
VDDSD
VSSSD
PCI_STOP#
CPU_STOP#
PD#/VTT_PWRGD
R502 33
Y6
14.318MHz
1 2
R508 33
R501 33
C564
0.01UF
R425
22
T
T
T
R492 33
C595 10PF(R)
R394
475_1%
R424
22
D22
1SS355
AC
RP61
4P2R-0
1
2 3
4
RP60 4P2R-01
2 3
4
RP69 4P2R-01
2 3
4
RP73
4P2R-0
1
2 3
4
T
T
RP74 4P2R-0
1
2 3
4
Main Clock Generator
By-Pass Capacitors
Place near to the Clock
Outputs
Clock Outputs
Damping Resistors
Place near to the
Clock Buffer (DDR)
By-Pass Capacitors
Place near to the Clock Buffer
Frequency
Selection
L L
H L
BSEL1 BSEL0 Function
H H
L H
ICS 93722
CY 28342
ICS 952001
14.381MHZ
48 MHZ
NEAR DDR SODIMM
PLEASE PLACE IN COMP SIDE
AND NEAR TOGETHER
FS4 FS3 FS2 FS1 FS0
0 0 0 1 1
CPU SDRAM ZCLK AGP PCI
100M 133M 66M 66M 33M
0 0 0 0 1 100M 100M 66M 66M 33M
CY28352