Service manual
C – 5
C
IRCUIT
D
IAGRAMS
C. CIRCUIT DIAGRAMS
System Board (71-P2200-006) - Sheet 4 of 19
LP-200
6
630-2, 630-3 (PCI/IDE/PWR)
ÂÅ ¤Ñ ¹q ¸£ CLEVO CO.
419T uesday, June 20, 2000
Title
Size Docum ent Num ber Rev
Dat e: Sheet of
+1.8V
+3V
+3V
+3V
+1.8V
+3V
+3V
+3V
+3V
PREQ#2 ICHRDYA
PREQ#1 IDEREQA
PREQ#0 IDE-IRQ14
CB LI D A
IDEIOR#A
PG NT #0
C/BE#3
C/BE#2
C/BE#1
C/BE#0
INT#A
ICHRDYB
IDEREQB
INT#D IDE-IRQ15
CB LI D B
IDEIOR#B
IDEIOW#B
IDACK#B
IDESAB2
IDESAB1
IDESAB0
IDECSB#1
IDECSB#0
AD[ 0. .31]
C/ BE#[ 0. .3]
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Z0403
IDACK#A
IDEIOW#A
IDECSA#1
IDESAA1
IDESAA0
IDESAA2
IDECSA#0
MD44
MD43
MD42
MD41
IDEDA0
IDEDB2
IDEDB3
I DE DA[ 0. .15]
IDEDA9
IDEDA10
IDEDA8
IDEDA7
IDEDA6
IDEDA3
IDEDB1
I DE DB[ 0. .15]
IDEDA11
IDEDB11
IDEDB12
IDEDB13
IDEDA14
IDEDA5
IDEDA4
IDEDB10
IDEDB5
IDEDA2
IDEDA13
IDEDB4
IDEDA15
IDEDB0
IDEDB6
IDEDB7
IDEDB9
IDEDB15
IDEDB8
IDEDB14
IDEDA1
IDEDA12
630PCLK
DEVSEL#
SER R#
IRDY#
TRDY#
FRAME#
PLOCK#
PA R
ST O P#
INT#B
INT#C
Z0405
Z0407
Z0406
Z0404
MD38
MD56
MD55
MD59
MD61
MD62
MD57
MD58
MD60
MD54
MD[ 0..63]
PG NT #1
PG NT #2
SER R#
ST O P#
D EVS EL# PER R#
PLOCK#
I RDY #
INT#C
INT#B
INT#A
INT#D
PREQ#2
PREQ#0
PREQ#1
F RAM E#
630PCLK
TRDY#
Z0401Z0412
Z0402
PG NT #2
PG NT #1
PG NT #0
T Z0404
T Z0403
T Z0402
T Z 0401
+
CT 1 5
10u/ 16V
CA63
0. 1u
CB15
1000p
R81
BEA D_0805
R30 4. 7K _R
R32 4. 7K _R
R33 4. 7K _R
R34 4. 7K _R
R36 4. 7K _R
R38 4. 7K _R
R78 4. 7K _R
R39 4. 7K _R
R41 4. 7K _R
SW2
4X2 DI PSWIT CH_R
1
2
3
4
8
7
6
5
RN61
8P4R x 4.7K_R
1 8
2
3 6
4 5
7
R35 4. 7K _R
RP19
10P8R x 2. 7K
1
2
3
4
5
10
6
7
8
9
RP18
10P8R x 2. 7K
1
2
3
4
5
10
6
7
8
9
C118
10p
U14B
SI S-630
B18
E17
C1 8
E6
D1 5
D1 4
E13
A10
B12
A13
F14
B13
A12
C1 3
D1 3
AF8
AG13
AE11
AE15
AD12
AF15
F16
C1 7
D1 7
AJ9
AH9
AG8
AF13
AE8
AJ12
AH8
AH13
AG9
AJ8
AF9
AD10
AE9
AD8
AF6
AF7
AG 5
AE7
AE5
AF5
AD6
AE6
AG 6
AJ6
AG 7
AH7
AH12
B10
D10
E11
C10
C11
B11
E12
A11
D12
C12
C14
E14
B14
A14
A15
E15
B15
C15
F15
A16
B16
C16
E16
D16
A17
B17
D11
F12
AG 12
AF12
AH11
AG 11
AJ10
AH10
AF10
AE10
AE13
AG 10
AD14
AF11
AE14
AJ11
AD15
AJ7
AE16
AJ13
AF14
AH14
AG14
AE12
AD16
E10
A9
B9
C9
AJ14
L5
AH15
K5
J5
J4
J3
PREQ#[2]
PREQ#[1]
PREQ#[0]
PCIRST #
C/ BE#[3]
C/ BE#[2]
C/ BE#[1]
C/ BE#[0]
PAR
F RAM E#
IRDY#
TRDY#
ST O P#
DEVSEL#
PLOCK#
ICHRDYA
ICHRDYB
IDREQ[A]
IDREQ[B]
IIRQA
IIRQB
PG NT #[2]
PG NT #[1]
PG NT #[0]
I DECSA #[1]
I DECSA #[0]
IIOR#[A]
IIOR#[B]
IIOW#[ A]
IIOW#[ B]
IDACK#[A]
IDACK#[B]
IDSAA[2]
IDSAA[1]
IDSAA[0]
IDA14
IDA13
IDA12
IDA11
IDA10
IDA9
IDA8
IDA7
IDA6
IDA5
IDA4
IDA3
IDA2
IDA1
IDA0
IDB15
AD7
AD4
AD5
AD6
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD9
AD8
IDB0
IDB1
IDB2
IDB3
IDB4
IDB5
IDB6
IDB7
IDB8
IDB9
IDB10
IDB11
IDB12
IDB13
IDB14
IDA15
IDSAB[2]
IDSAB[1]
IDSAB[0]
I DECSB #[1]
I DECSB #[0]
CB LI D A
CB LI D B
AD3
AD2
AD1
AD0
PCICLK
SERR#
IDE AVDD
INTA#
INTB#
INTC#
INTD#
U14C
SI S-630
M12
M13
M14
M15
M16
M17
M18
N12
N13
N14
N15
N16
N17
N18
P12
P13
P14
P15
P16
P17
P18
R12
R13
R14
R15
R1 6
R1 7
R1 8
T12
T13
T14
T15
T16
T17
T18
U1 2
U1 3
U1 4
U1 5
U1 6
U1 7
U1 8
V12
V13
V14
V15
V16
V17
V18
AA9
Y9
W9
L21
K21
J21
J20
J19
AA19
AA10
AA11
AA20
AA21
W21
Y21
J13
J14
J15
J16
J17
J18
M9
M21
N9
N2 1
P9
P21
R9
R2 1
T9
T21
U9
U2 1
V9
V21
AA12
AA13
AA14
AA15
AA16
AA17
AA18
H14
H15
H16
N8
P8
P22
R8
R22
T8
T22
AB14
AB15
AB16
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
VS S
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
PVD D
R225 300
R7 6
15
U17D
74HC32
12
13
11
147
U17C
74HC32
9
10
8
147
R313
0
CA51
0. 1u
CA70
0. 1u
CA52
4. 7u/ 10V_1206
CA65
0. 1u
CA46
0. 1u
CA47
0. 1u
CA56
0. 1u
CA66
0. 1u
CA78
0. 1u
CA60
0. 1u
CA75
0. 1u
CA55
0. 1u
CA62
0. 1u
CA54
0. 1u
CA64
0. 1u
CA61
0. 1u
CA73
0. 1u
CA74
0. 1u
CA59
0. 1u
+
CT 1 1
10u/ 16V
RN77
8P4R x 2. 7K
1
2
3
4
7
6
5
8
T 104
T 105
T 107
T 106
CA221
0. 1u
CA223
0. 1u
CA224
0. 1u
CA222
0. 1u
CA225
0. 1u
+
CT 6 1
10u/ 16V
+
CT 1 0
10u/ 16V
+ 1.8V 12, 18
ICHRDYA 10
IDEREQA 10
IDE-IRQ14 10
CBLIDA 10
ID EI OR#A 10
IDEIOW#A 10
IDACK#A 10
ID ECSA#1 10
ID ECSA#0 10
IDESAA0 10
IDESAA1 10
IDESAA2 10
ID EI OR#B 10
IDEIOW#B 10
IDACK#B 10
IDESAB2 10
IDESAB1 10
IDESAB0 10
ID ECSB#1 10
ID ECSB#0 10
ICHRDYB 10
IDEREQB 10
IDE-IRQ15 10
CBLIDB 10
I DE DA[ 0. .15] 10
I DE DB[ 0. .15] 10
AD[ 0. .31]11, 19
C/ BE#[ 0. .3]11, 19
INT#A11
INT#B11
INT #C19
INT #D9
630PCLK6
PLOCK#11
PCIRST #19, 10, 19
I RDY #11, 19
SER R#11, 19
DEVSEL#11, 19
ST O P#11, 19
FRAME#11, 19
TRDY#11, 19
PA R11, 19
MD[0. .63]3, 7,10
+ 3V 2, 3, 5, 6,7, 8, 9,10, 11, 12,13, 14, 15, 16,18, 19
PGNT #219
PGNT #1
PGNT #011
PREQ#011
PREQ#1
PREQ#219
PERR# 11, 19
PCIRST#211,12, 13
(FOR INT ERNAL PLL)
MD61: S DRAM DLL Enable
MD60: CPU DLL Enable
MD62: PCI PLL E nable
(Default 00)
(Default 00)
1: Dis able0:E nable
1: Dis able0:E nable
1: Dis able0:E nable
MD[59. .58] : SDRAM DLL DRC[ 1. .0]
MD[57. .56] : CPU DLL DRC[ 1..0]
MD38: V GA I nt errupt Funct ion
1:E nable0: Dis able
(Default 00)
MD[55..54] : PCI PLL DRC[1. .0]
These H/W traps have inter nal pull - down resi stors.
SiS-630 POWER
IDE Interface
PCI Interface
SiS-630
A3
71-P2200-006
CPU Freq uency Rat io Select
1/2 (200 MHz)
1/3 (300 MHz)
1/4 (400 MHz)
1/5 (500 MHz)
2/5 (250 MHz)
2/7 (350 MHz)
2/9 (450 MHz)
2/11 (550MHz)
1/6 (600 MHz)
1/7 (700 MHz)
1/8 (800 MHz)
Re s e r v e d
2/13 ( 650 MHz)
2/15 ( 750 MHz)
2/3 (150 MHz)
1/2 (200 MHz)
MD44 MD43 MD42 MD41
(IGNNE#)(A20M#)(I NT R)(NMI)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1