Service manual
C – 2
CIRCUIT DIAGRAMS
C. CIRCUIT DIAGRAMS
System Board (71-P2200-006) - Sheet 1 of 19
LP-200
6
Socket-370 PIII CPU
ÂÅ ¤Ñ ¹q ¸£ CLEVO CO.
119T uesday, June 20, 2000
Title
Size Docum ent Number Rev
Date : Sheet
of
V_CMO S
CP UVRE F
VT T +2.5V
V_CMOS
V_CMOS
V_CORE
V_C MO S
VT T
V_CMO S
VT T
CP UV RE F
+2.5V
VT T
VT T
+2.5V
VT T
V_CMO S
HT DI
FLUSH#
PREQ # HTMS
CPU SL P#
HT RS T #
FERR#
HT DO
PIC D0
HT CKPIC D1
Z0104
CPUC LK
PICCLK Z0106
Z0105
A20M#
SMI#
INIT# STPCLK#
IGNNE# NMI
INTR
F LUS H#
PREQ#
HD#22
HD#50
HA# 9
HA# 16
T Z0113
IGNNE#
PICCLK
T Z0136
T Z0122
T Z0135
HD#7
HD#12
HD#16
HD#27
HD#35
HD#38
HA# 15
HA# 24
HA# 31
BSEL1#
T Z0119
T Z0112
VI D2
HT DI
HT RST #
T Z0134
T Z0129
T Z0114
T Z0121
T Z0105
T Z0108
HD#5
HD#31
HD#39
HD#54
HA# 4
HA# 17
HREQ # 2
SLEWCT RL
T Z0117
T Z0115
HD#19
HD#43
HD#44
HD#59
HA# 6
HD#14
HD#28
HD#37
HD#51
HA# 23
HA# 26
HREQ # 0
HREQ #[0. . 4]
HT DO
SMI#
PWRG OO D
T Z0106
HD#4
HD#10
HD#46
HD#60
HA# 7
HT CK
HD#0
HD#9
HD#61
HA# 20
HA# 25
HREQ # 4
HD#[0..63]
T Z0128
T Z0109
HD#3
HD#11
HD#23
HD#49
HA# 18
HA# 29
HREQ # 3
STPCLK#
FERR#
HD#32
HD#40
HD#58
HD#63
HA# 5
HA# 10
HA# 11
HA# 27
T Z0118
Z0102
T Z0125
T Z0132
T Z0131
T Z0127
T Z0116
HD#24
HD#29
HD#30
HD#52
HA# 3
HA# 19
CLK RE F
T Z0102
INTR
PIC D1
PIC D0
T Z0123
T Z0120
T Z0126
T Z0104
HD#15
HD#26
HA# 12
HA# 14
HA# 28
HREQ # 1
A20M#
T Z0138
T Z0133
T Z0111
HD#17
HD#21
HD#25
HD#33
HD#45
HD#53
RTT CT RL
VI D3
HT MS
NMI
T Z0137
HD#1
HD#13
HD#41
HD#42
HA# 13
HA# 21
Z0103
Z0101
T Z0110
HD#2
HD#34
HD#62
BSEL0#
Z0107
HD#18
HD#20
HD#48
HD#55
HD#57
HA# 30
VI D1
VI D0
INIT#
CPU S LP#
T Z0103
HD#8
HD#56
HA# 22
HA#[3. .31]
T Z0107
T Z0124
T Z0130
T Z0101
HD#6
HD#36
HD#47
HA# 8
T Z0139
T Z0141
T Z0143
T Z0142
T Z0140
T Z 0145
T Z 0146 T Z0 144
T Z 0151
T Z 0150
T Z 0149
T Z 0148
T Z 0147
T Z 0152
R25 9 51 0
R24 0 1K
R25 6 68 0
C8 6
4. 7u/ 1 6V
R24 4 1K
R20 5 51
L33
33uH
1 2
+
C19 5
22u/10V_1206
RN8
8P 4R x 330
1 8
2
3 6
4 5
7
RN49
8P 4R x 150
1 8
2
3 6
4 5
7
CB3
1000 p
CB1 9
1000p
CB4
1000 p
CB6
1000 p
CB7
1000 p
CA1 8
0. 1 u
CB2 0
1000p
R4 4
150 1%
L31
0
1 2
CB5
1000 p
CB8
1000p
CT 45
10u/ 16V
R2 3 9
110 1%
CA 23
0. 1 u
CA 15 4
0. 1u
CA1 72
0. 1u
CA1 7
0. 1u
CA1 5
0. 1u
CA1 45
0. 1u
CA1 38
0. 1u
CA1 50
0. 1u
C19 8
10p
C19 4
10p
CA1 30
0. 1 u
CA1 82
0. 1 u
CA1 76
0. 1 u
CA1 74
0. 1 u
CA 18 0
0. 1 u
CT 3 5
10u/16V
CB2 8
1000 p
CB1 0
1000p
CB9
1000p
CT 6
10u/ 16V
CA2 6
0. 1 u
CA1 73
0. 1 u
CA4 8
0. 1 u
CA1 71
0. 1 u
CA2 2
0. 1u
CA1 75
0. 1u
CA4 4
0. 1u
CA1 6
0. 1u
CA1 32
0. 1 u
CA1 31
0. 1 u
CA1 4
0. 1 u
CA1 33
0. 1 u
CA1 34
0. 1 u
CA1 35
0. 1u
CA1 36
0. 1u
R2 5 5
15
R2 4 2
15
R232 56
RP1 7
10P 8R x 470
1
2
3
4
5
10
6
7
8
9
R2 4 3
110 1%
R49
150
R2 1 8
75 1%
R47
150
U3A
INTEL_PIII
W3 7
AN19
AN25
X4
AN17
AK28
AH22
AH26
AD6
R6
AN31
AL23
AL25
AN27
AL27
AK20
AH14
AN29
AL17
AL19
AH18
AH16
AK18
AD4
AA3
Z4
AK6
AA1
Y3
AF6
AB4
AB6
AE3
AJ1
AC3
AG 3
Z6
AE1
AN7
AL5
AK14
AL7
AN5
AK10
AH6
AL9
AH10
AL15
AN9
AH8
AH12
AK8
E25
F16
A27
A25
C17
C23
A19
C27
C19
C21
A23
D16
A13
C25
C13
A17
A15
A21
C11
A11
A7
D12
D14
C15
D10
D8
A9
C9
B2
C7
C1
F6
C5
J3
A3
A5
F12
E1
E3
K6
G3
F8
G1
L3
H6
P4
R4
H4
U3
N3
L1
Q1
M4
Q3
P6
S1
J1
T6
S3
U1
M6
N1
T4
W1
AC1
AC37
AF4
AK16
AK24
AK30
AL11
AL13
AL21
AN11
AN13
AN15
AN21
AN23
B36
C29
C31
C33
E23
E29
E31
F10
G35
G37
L33
N33
N35
N37
Q33
Q35
Q37
S33
S37
U35
U37
V4
W3
W35
X6
Y1
E21
E27
R2
S35
X2
J33
J35
L35
A35
J37
AK2 6
AH30
AJ 35
AL3 3
E35
AJ 33
AE3 7
AE3 5
AG 37
AN33
V6
F18
E33
AK2 2
K4
AK1 2
L37
AG 33
C3 5
E37
G33
AC35
AE3 3
C3 7
AG 1
W3 3
U3 3
AL31
AL29
M36
AN35
AN37
AK3 2
AL3 5
AM 36
AL3 7
AJ 37
AG 35
AH28
AH20
AH4
A29
A31
A33
AA33
AA35
AD36
Z36
AB3 6
AM2
AJ 31
Y33
BCLK
DEF E R#
TRDY#
RESET 2#
BPRI #
RS#[2]
RS#[1]
RS#[0]
VREF5
VREF3
ADS#
HI T M #
HI T #
DRDY #
DBS Y #
LOCK#
BNR#
BR0#
REQ # [ 4]
REQ # [ 3]
REQ # [ 2]
REQ # [ 1]
REQ # [ 0]
A#[31]
A#[30]
A#[29]
A#[28]
A#[27]
A#[26]
A#[25]
A#[24]
A#[23]
A#[22]
A#[21]
A#[20]
A#[19]
A#[18]
A#[17]
A#[16]
A#[15]
A#[14]
A#[13]
A#[12]
A#[11]
A#[10]
A#[9]
A#[8]
A#[7]
A#[6]
A#[5]
A#[4]
A#[3]
D#62
D#63
D#61
D#60
D#59
D#58
D#57
D#56
D#55
D#54
D#53
D#52
D#51
D#50
D#49
D#48
D#47
D#46
D#45
D#44
D#43
D#42
D#41
D#40
D#39
D#38
D#37
D#36
D#35
D#34
D#33
D#32
D#31
D#30
D#29
D#28
D#27
D#26
D#25
D#24
D#23
D#22
D#21
D#20
D#19
D#18
D#17
D#16
D#15
D#14
D#13
D#12
D#11
D#10
D#9
D#8
D#7
D#6
D#5
D#4
D#3
D#2
D#1
D#0
A#[33]
RS P#
A#[35]
VT T
AERR#
RES ERVE D
AP0#
VT T
VT T
VT T
AP1#
VT T
VT T
RP#
BINIT #
DEP5#
DEP1#
DEP0#
VT T
DEP6#
DEP4#
RES ERVE D
VT T
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
VT T
VT T
VT T
VT T
BERR#
A#[34]
TESTHI
A#[32]
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
RES ERVE D
PICCLK
PICD[0]
PICD[1]
PRDY #
PREQ #
PWRGOO D
SLP#
SMI #
TCK
BPM#[ 1]
BSEL0
F LUS H#
IERR#
IGNNE#
TRST#
VREF4
VREF1
VREF0
VREF7
VREF2
VREF6
LI NT [1] /NMI
INIT #
BPM#[ 0]
BP#[3]
BP#[2]
FERR#
A20M#
CP UP RE S#
EDGCT RL/ VRSEL
PLL1
PLL2
THERMDP
THERMDN
LINT[0]/INT R
TDI
TDO
TMS
VID [0]
VID [1]
VID [2]
VID [3]
STPCLK#
THERMTRIP#
VT T
RESET #
DEP7#
DEP3#
DEP2#
VT T
VT T
VCC_1.5V
VCC_2.5V
VCC_CMOS
GND
BSEL1
G N D/ CL K R E F
T30
T31
T32
T33
T34
T35
T39
T41
T37
T36
T38
T40
T43
T42
T44
T46
T45
T47
T48
T50
T49
T51T52
T53
T80
T54
T55
T56
T57
T59
T58
T60
T61
T62
T63
T65
T64
T66
T68 T69
T67 T71
T73 T72
T70 T76
T74 T75
T77
T78
T79
C346
0. 1u
C34 7
0. 1 u
C34 8
0. 1 u
C34 9
4. 7u_120 6
+2.5V 6,9,12,18
DXN2
DXP2
CP URS T #2, 3
CPUC LK6
RS# 22, 3
RS# 12, 3
RS# 02, 3
BPRI #2, 3
HT RDY #2, 3
BREQ0#2, 3
HLO C K#2, 3
DEF E R#2, 3
HI T M #2, 3
HI T #2, 3
DBSY #2, 3
DRDY #2, 3
BNR#2, 3
ADS#3
HA#[3. .31] 2,3
HD#[0..63] 2, 3
HR EQ # [ 0. . 4] 2, 3
P ICC LK 13
SMI # 3
INIT# 3
CPU S LP # 3
IGNNE# 3
STPCLK# 3
NMI 3
PWRGOO D 12
INTR 3
A20M# 3
FERR# 3
BSEL0# 6
BSEL1# 6
VID[0. .3] 18
VT T 2,3, 18
V_CORE 2,18
V_CMO S
SOCKET 370
1. 30
1. 35
1. 40
1. 45
1. 50
1. 55
1. 60
1. 65
1. 70
1. 75
1. 80
1. 85
1. 90
1. 95
2. 00
2. 05
VCC_COREVI D3 VI D2 VI D1 VID0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
F or Fut ure Compat ibil it y Upgrat e
PLACE NEAR T HE MENDOCINO
(FOR VREF0 T O VREF7)
71-P2200-006
A3
SYSTEM BOARD