Service manual
Schematic Diagrams
B - 42 POWER SYSTEM
B.Schematic Diagrams
POWER SYSTEM
Sheet 41 of 63
POWER SYSTEM
PQ93
MTN7002ZHS3
G
DS
PQ8
MTN7002ZHS3
G
DS
D02-0929J
Modify 3.3V
VDD3
VCCD_01_PG46
C147 *0.1u_10V_X5R_04
U5
74AHC1G08GW
1
2
5
4
3
VDD3
DRAM_PWROK_ANDGATE 5
PCH_SYSPWROK
R115 4.7K_04
R112 0_04
3.3V
R103
0_04
VR_RDY6,52
3.3V
VCCD_23_PG46
PCH_SYSPWROK 25
R123 0_04
PCH_DRAM_PWRGD25
R119 4.7K_04
3.3VS
R104
1K_04
PQ15
2N3904
B
E C
DRAM_PWR_OK
R120 *0_04
R932 *0_04
R934
1K_04
R931 *0_04
R102 *10mil_NP_04
R933 1.2K_04
C348
0.47u_16V_Y 5V_06
LGSPARE_0_R
PCH_PWROK
H
H
H
L
H
L
A
OutputInput
Y
R212
10K_04
B
H
H
R206
10K_04
V_CPU_VTT
VDD3
R217
10K_04
VDD3
Qn+1
VDD3
R220
10K_04
VDD3 V_CPU_VTT
R215
10K_04
VDD3
Qn*+1
VDD3
LGSPARE_1_R
LGSPARE_1 5
LGSPARE_0 5
SUSC#25,33,46
PCH_GP6525
H
L
PCH_GP6525
U13
74AUP1G74GM
D
2
CP
1
VCC
8
RD
6
Q
3
Q*
5
SD*
7
GND
4
CK_PWR_TOGGLE
U12
74AHC1G32GW
4
53
1
2
PCH_GP6525
U8
74AUP1G74GM
D
2
CP
1
VCC
8
RD
6
Q
3
Q*
5
SD*
7
GND
4
H
L
U11
74AUP1G74GM
D
2
CP
1
VCC
8
RD
6
Q
3
Q*
5
SD*
7
GND
4
74AUP1G74GM
CP clock input
D data input
Q* complement output
Q true output
RD asynchronous reset input (active LOW)
SD asynchronous set input (active LOW)
VDD3
PCH_GP2825
PCH_GP6425
VDD5
CHANGE_REQ_BIT_R
R262
10K_04
L
L
L
CK_PWR_TOGGLE
R263
1K_04
H
SUSC#25,33,46
H
L
PCH_GP2625
H
H
WDT_RST_N
PQ9
MTN7002ZHS3
G
DS
1A
PQ10
AO3409
G
D S
Input
RDSD
Output
VDD3
R251
4.7K_04
VDD5
VDD_CLK
R258
4.7K_04
CP
VDD3
U14
74AUP1G74GM
D
2
CP
1
VCC
8
RD
6
Q
3
Q*
5
SD*
7
GND
4
W DT_ RS T_R
VDD3
R286
4.7K_04
D
74AHC1G32 GW
B data input
A data input
Y data output
H
¡ô
¡ô
CK_PWR_TOGGLE
H
SYS_PWROK
R435
10K_04
PQ92
MTN7002ZHS3
G
DS
C522
0.22U_06
R458
10K_04
VDD3
PWRGD_3V
R465
100K_04
PQ14
MTN7002ZHS3
G
DS
R466
*100K_04
V_CPU_PLL
PWRGD_3V 24,25
0718J
for timing
PQ7
MTN7002ZHS3
G
DS
0722-J
Modify
VR_RDY
0722-J
Modify