Service manual

Schematic Diagrams
B - 36 Power VGFX_CORE
B.Schematic Diagrams
Power VGFX_CORE
Sheet 35 of 40
Power VGFX_Core
15A(7A)
PR8
8 0 . 6 K _ 1% _0 4
PR22
7. 5 K _1 % _0 4
PC 134
220p_50V_N PO_04
PC17
0. 2 2 u_ 5 0V _ 06
PR42
10K_1% _04
PR154
*2 .2_ 0 6
+
PC129 220u_4V_V_B
PC 1 3
2. 2 u_ 1 6V _ X5 R _ 0 6
PR 36 100_1%_04
PR47 *1 K_0 4
PR156
160K_1%_04
PR 4 8 * 1 K _ 0 4 PR 56 1K _ 04
PR3
332K_1% _06
PL3
1.0UH_10*10*4.5
1 2
PR 4 0
*10K_1%_04
PR45 1 K_04
PR50
47 0 _0 4
PR46 1 K_04
PR 39 100_1%_04
P R 57 1 K _0 4
PC20 220p_50V_NPO_04
PR158
110K_1% _06
PR34
1K _ 1% _ 04
PC13 7 * 0.1u_10V_X5R _04
PQ24
MD S 26 55
4
62 5 73
1
8
PC 1 8
47 p_ 5 0V _ N P O _ 04
PC96 *4 .7u _25 V_X5R_08
PC25
0. 1 u _5 0V _ Y 5 V _0 6
PJ 15
OPE N _8 A
1 2
PR55 1K_04
PR 35
0_06
PR 3 2
0_ 04
PR54 *1 K_0 4
PR 44 * 1K_0 4
PC19
470p_50V_X7R_04
PR21
0_ 04
PR38
*10K_1%_04
PC24
1000p_50V_X7R_04
PJ 3 40mil
12
PC128
* 2 20 0 p_ 5 0V _ X 7R _0 4
PU1
AD P3211
GPU
7
PW RG D
1
IM ON
2
CLKEN#
3
FBRTN
4
FB
5
COMP
6
IL IM
8
IR EF
9
RPM
10
RT
11
RAMP
12
LLIN E
13
CSREF
14
CSF B
15
CSCOM P
16
VCC
24
BST
23
DRVH
22
SW
21
PVCC
20
DR VL
19
PG ND
18
AG ND
17
EN
32
VID0
31
VID1
30
VID2
29
VID3
28
VID4
27
VID5
26
VID6
25
AG ND
33
PR7
200K_1% _04
PC8
1500p_50V_06
PR 52 1K_04
PC85 4.7u_25V_X5R_08 P C 8 8 4 . 7u _2 5 V _X 5 R _ 08
PC 4 0.1u_50V_Y5V_06
PQ19
MD S2 6 59
4
62 5 73
1
8
PR157
180K_1% _04
PR 4 1
4.7K_1%_04
+
PC130 *220u_4V_V_B
PR59 1K_04
PC7
1000p_50V_X7R _04
PR43 1K_04
PR53 * 1K_04 PR51 *1 K_0 4
PJ2 40m il
12
PR 49 * 1K_04
PR37
10_06
PR6 1K_1% _04
PC21
10 0 0p _ 50 V _X 7 R _ 04
PC138 * 0 . 01 u _ 5 0V _ X 7R _0 4
PQ25
MDS2655
4
62 5 73
1
8
RT2
100K_NTC_06_B
12
PR33 20K_1% _04
PR2
422K_1%_06
PR31
*0_04
PD10
SK34SA
A C
PR 5 8 10K_04
PC5 * 0.01u_50V_X7R_04
GPU VCCSENSE 7
GPU VSSSEN SE 7
DFG T_ VID_ 47
DFG T_ VID_ 17
DFG T_ VID_ 27
DFG T_ VID_ 07
GF X _IM ON7
DFG T_ VID_ 57
DFG T_ VID_ 67
DFG T_ VID_ 37
3.3VS
1. 1VS_VTT
3. 3 V S
VGFX_CO RE
VIN
GPU
5VS
3. 3 V
5VS
5VS
GPU
G N D _ 32 11
GND_3211
G ND_3211GND_3211
VIN
3.3 VS
GN D_3211
G ND_32 1 1
G N D _ 32 11
GND _3211
G N D _ 32 11
VIN12,30,31,32,33,34,36,37
5VS2, 1 3 ,17,20,21,26,27,30,31,36
1.1VS_VTT
1.5V4,9,10,11,21,23,27,29,31,33,36
3.3VS2,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,36
VGFX_CO RE7
1.1VS_VTT2,4,6,7,14,15,16,19,20,21,34,36
DFGT_ VR_ EN7
3.3V3, 4 , 12 , 1 4, 1 5 ,16,18,19,20,21,23,24,25,29,30,31,33,34
VGFX_ VO RE_PG16
distr ibute evenly between N side and S si de,
prefer ably on secondar y side.
3 2 11 _D R V L
CPU
GPU1
GPU
0
App. Place RTH1 close to
i n du ct o r on th e sa m e la y er
3 2 11 _D R V H
??JUMP? ?
PJ4 FOR CV???
3211_CSCO MP
DFG T_VR_ E N
VGFX_CORE
3 2 11 _C S C O M P
3 2 11 _S W
3211_CSCO MP
(0. 7V ~1 .77V )
DFG T_VID_ 3
DFG T_VID_ 4
DFG T_VID_ 5
DFG T_VID_ 0
DFG T_VID_ 1
DFG T_VID_ 2
DFG T_VID_ 6
PC23
1u_6.3V_X5R_04
32 11 _ C L K E N #